SCLS087F December 1982 – June 2021 SN54HC21 , SN74HC21
PRODUCTION DATA
請參考 PDF 數據表獲取器件具體的封裝圖。
Standard CMOS inputs are high impedance and are typically modeled as a resistor from the input to ground in parallel with the input capacitance given in the Section 6.4. The worst case resistance is calculated with the maximum input voltage, given in the Section 6.1, and the maximum input leakage current, given in the Section 6.4, using ohm's law (R = V ÷ I).
Signals applied to the inputs need to have fast edge rates, as defined by the input transition time in the Section 6.2 to avoid excessive current consumption and oscillations. If a slow or noisy input signal is required, a device with a Schmitt-trigger input should be used to condition the input signal prior to the standard CMOS input.