SCES587D AUGUST 2004 – November 2015 SN74AVCH16T245
PRODUCTION DATA.
- 1 Features
- 2 Applications
- 3 Description
- 4 Revision History
- 5 Description (continued)
- 6 Pin Configuration and Functions
-
7 Specifications
- 7.1 Absolute Maximum Ratings
- 7.2 ESD Ratings
- 7.3 Recommended Operating Conditions
- 7.4 Thermal Information
- 7.5 Electrical Characteristics
- 7.6 Switching Characteristics: VCCA = 1.2 V
- 7.7 Switching Characteristics: VCCA = 1.5 V ± 0.1 V
- 7.8 Switching Characteristics: VCCA = 1.8 V ± 0.15 V
- 7.9 Switching Characteristics: VCCA = 2.5 V ± 0.2 V
- 7.10 Switching Characteristics: VCCA = 3.3 V ± 0.3 V
- 7.11 Operating Characteristics
- 7.12 Typical Characteristics (TA = 25°C)
- 8 Parameter Measurement Information
- 9 Detailed Description
- 10Application and Implementation
- 11Power Supply Recommendations
- 12Layout
- 13Device and Documentation Support
- 14Mechanical, Packaging, and Orderable Information
封裝選項
請參考 PDF 數據表獲取器件具體的封裝圖。
機械數據 (封裝 | 引腳)
- DGG|48
- DGV|48
散熱焊盤機械數據 (封裝 | 引腳)
訂購信息
10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.
10.1 Application Information
The SN74AVCH16T245 device can be used in level-shifting applications for interfacing devices and addressing mixed voltage incompatibility. The SN74AVCH16T245 device is ideal for data transmission where direction is different for each channel.
10.2 Typical Application
Figure 12. Typical Application Schematic
10.2.1 Design Requirements
This device uses drivers which are enabled depending on the state of the DIR pin. The designer must know the intended flow of data and take care not to violate any of the high or low logic levels. Unused data inputs are must not be floating, as this can cause excessive internal leakage on the input CMOS structure. Tie any unused input and output ports directly to ground.
For this design example, use the parameters listed in Table 3.
Table 3. Design Parameters
| DESIGN PARAMETER | EXAMPLE VALUE |
|---|---|
| Input voltage range | 1.2 V to 3.6 V |
| Output voltage range | 1.2 V to 3.6 V |
10.2.2 Detailed Design Procedure
To begin the design process, determine the following:
10.2.2.1 Input Voltage Ranges
Use the supply voltage of the device that is driving the SN74AVCH16T245 device to determine the input voltage range. For a valid logic high the value must exceed the VIH of the input port. For a valid logic low the value must be less than the VIL of the input port.
10.2.2.2 Output Voltage Range
Use the supply voltage of the device that the SN74AVCH16T245 device is driving to determine the output voltage range.
10.2.3 Application Curve
Figure 13. Translation Up (1.2 V to 3.3 V) at 2.5 MHz