ZHCSR19G December 2002 – September 2022 SN65HVD20 , SN65HVD21 , SN65HVD22 , SN65HVD23 , SN65HVD24
PRODUCTION DATA
The driver and receiver behavior for different input conditions are shown in Table 10-1 and Table 10-2, respectively.
| DEVICE | INPUT | ENABLE | OUTPUTS | |
|---|---|---|---|---|
| D | DE | A | B | |
| SN65HVD2[0,1,2] | H | H | H | L |
| L | H | L | H | |
| X | L | Z | Z | |
| X | OPEN | Z | Z | |
| OPEN | H | H | L | |
| SN65HVD2[3,4] | H | H | H | L |
| L | H | L | H | |
| X | L | Z | Z | |
| X | OPEN | Z | Z | |
| OPEN | H | L | H | |
| DIFFERENTIAL INPUT VID = (VA – VB) | ENABLE RE | OUTPUT R |
|---|---|---|
| 0.2 V ≤ VID | L | H |
| –0.2 V < VID < 0.2 V | L | H(2) |
| VID ≤ –0.2 V | L | L |
| X | H | Z |
| X | OPEN | Z |
| Open circuit | L | H |
| Short Circuit | L | H |
| Idle (terminated) bus | L | H |
Figure 10-3 Logic Diagram