ZHCSRU6F May 2002 – March 2023 SN65HVD05 , SN65HVD06 , SN65HVD07 , SN75HVD05 , SN75HVD06 , SN75HVD07
PRODUCTION DATA
The differential receiver is “failsafe” to invalid bus states caused by:
Receiver failsafe is accomplished by offsetting the receiver thresholds so that the “input indeterminate” range does not include zero volts differential. To comply with the RS-422 and RS-485 standards, the receiver output must output a High when the differential input VID is more positive than +200 mV, and must output a Low when the VID is more negative than -200 mV. The receiver parameters which determine the failsafe performance are VIT+ and VIT- and VHYS. As seen in the Receiver Electrical Characteristics table, differential signals more negative than -200 mV will always cause a Low receiver output. Similarly, differential signals more positive than +200 mV will always cause a High receiver output.
When the differential input signal is close to zero, it will still be above the VIT+ threshold, and the receiver output is High. Only when the differential input is more negative than VIT- will the receiver output transition to a Low state. So, the noise immunity of the receiver inputs during a bus fault condition includes the receiver hysteresis value VHYS (the separation between VIT+ and VIT- ) as well as the value of VIT+.