ZHCSJ04D november 2018 – october 2020 SN6505A-Q1 , SN6505B-Q1 , SN6505D-Q1
PRODUCTION DATA
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| VOLTAGE SUPPLY | ||||||
| I(Vcc) | Supply Current (2.8 V ≤ VCC ≤ 5.5 V) (SN6505A-Q1) | RL = 50 Ω | 1 | 1.4 | mA | |
| Supply Current (2.8 V ≤ VCC ≤ 5.5 V) (SN6505B-Q1 and SN6505D-Q1) | RL = 50 Ω | 1.56 | 2.3 | mA | ||
| IIH | Leakage Current on EN and CLK pin | EN / CLK = VCC | 10 | 20 | μA | |
| IDIS | VCC current for EN = 0 | 0.1 | μA | |||
| ILKG(D1) ILKG(D2) | Leakage Current on D1, D2 for EN=0 | Voltage of D1, D2 = VCC | 0.1 | μA | ||
| VCC+ (UVLO) | Positive-going UVLO threshold | 2.25 | V | |||
| VCC- (UVLO) | Negative-going UVLO threshold | 1.7 | V | |||
| VHYS (UVLO1) | UVLO threshold hysteresis | 0.3 | V | |||
| VIN(ON) | EN, CLK pin logic high threshold | 0.7 | VCC | |||
| VIN(OFF) | EN, CLK pin logic low threshold | 0.3 | VCC | |||
| VIN(HYS) | EN, CLK pin threshold hysteresis | 0.2 | VCC | |||
| CLK | ||||||
| FSW | D1, D2 average switching Frequency (SN6505A-Q1) | RL = 50 Ω to VCC; Refer to Figure 7-3 | 138 | 160 | 203 | Khz |
| D1, D2 average switching Frequency (SN6505B-Q1 and SN6505D-Q1) | RL = 50 Ω to VCC; Refer to Figure 7-3. | 363 | 424 | 517 | kHz | |
| F(EXT) | External clock frequency on CLK pin (SN6505A-Q1) | 100 | 600 | kHz | ||
| External clock frequency on CLK pin (SN6505B-Q1 and SN6505D-Q1) | 100 | 1600 | kHz | |||
| OUTPUT STAGE | ||||||
| DMM | Average ON time mismatch between D1 and D2 | RL = 50 Ω | 0% | |||
| R(ON) | Output switch on resistance | VCC = 4.5 V, ID1, ID2 = 1 A | 0.16 | 0.25 | Ω | |
| VCC = 2.8 V, ID1, ID2 = 1 A | 0.19 | 0.31 | Ω | |||
| VCC = 2.25 V, ID1, ID2 = 0.5 A | 0.21 | 0.45 | Ω | |||
| V(SLEW) | Voltage slew rates on D1 and D2 for SN6505A-Q1 | RL = 50 Ω to VCC; Refer to Figure 7-3 | 48 | V/μs | ||
| I(SLEW) | Current slew rates at D1 and D2 for SN6505A-Q1 | RL = 5 Ω through transformer; Refer to Figure 7-4 | 11 | A/μs | ||
| V(SLEWHF) | Voltage slew rates on D1 and D2 for SN6505B-Q1 and SN6505D-Q1 | RL = 50 Ω to VCC; Refer to Figure 7-3 | 152 | V/μs | ||
| I(SLEWHF) | Current slew rates at D1 and D2 for SN6505B-Q1 and SN6505D-Q1 | RL = 5 Ω through transformer; Refer to Figure 7-4 | 41 | A/μs | ||
| ILIM | Current clamp limit (2.8 V < VCC ≤ 5.5V ) | 1.42 | 1.75 | 2.15 | A | |
| Current clamp limit (2.25 V ≤ VCC ≤ 2.8 V) | 0.65 | 1.85 | A | |||
| THERMAL SHUT DOWN | ||||||
| TSD+ | TSD turn on temperature | 154 | 168 | 181 | °C | |
| TSD- | TSD turn off temperature | 135 | 150 | 166 | °C | |
| TSD- | TSD hysteresis | 13 | 17 | °C | ||