ZHCSIR4Q July 1995 – September 2018 SN54LVCH245A , SN74LVCH245A
PRODUCTION DATA.
請(qǐng)參考 PDF 數(shù)據(jù)表獲取器件具體的封裝圖。
The SN54LVCH245A octal bus transceiver is designed for a 2.7-V to 3.6-V VCC operation, and the SN74LVCH245A octal bus transceiver is designed for a 1.65-V to 3.6-V VCC operation. Inputs can be driven from either the 3.3-V or 5-V devices. This feature allows the use of these devices as translators in a mixed 3.3-V or 5-V system environment.
These devices are designed for asynchronous communication between data buses. These devices transmit data from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output-enable (OE) input can be used to disable the device, so the buses are effectively isolated.
These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs which prevents damaging current backflow through the devices when they are powered down. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. The bus-hold circuitry is part of the input circuit and is not disabled by OE or DIR, so use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.