ZHCSQ28E December 1982 – February 2022 SN54HC174 , SN74HC174
PRODUCTION DATA
請參考 PDF 數據表獲取器件具體的封裝圖。
These positive-edge-triggered D-type flip-flops have a direct clear (CLR) input.
Information at the data (D) inputs meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going edge of CLK. When CLK is at either the high or low level, the D input has no effect at the output.