ZHCSF42B May 2016 – August 2016 REF6125 , REF6130 , REF6133 , REF6141 , REF6145 , REF6150
PRODUCTION DATA.
12 Layout
12.1 Layout Guidelines
Figure 62 illustrates an example of a PCB layout for a data-acquisition system using the REF61xx. Some key considerations are:
- Connect low-ESR, 0.1-μF ceramic bypass capacitors between the VIN pin and ground.
- Place the REF61xx output capacitor (CL) and the ADC as close to each other as possible.
- Run two separate traces between VOUT_F, VOUT_S and the output capacitor, as shown in Figure 62.
- Short the GND_F and GND_S pins with a solid plane, and extend this plane to connect to the output capacitor CL, as shown in Figure 62.
- Use a solid ground plane to help distribute heat and reduces electromagnetic interference (EMI) noise pickup.
- Place the external components as close to the device as possible. This configuration prevents parasitic errors (such as the Seebeck effect) from occurring.
- Do not run sensitive analog traces in parallel with digital traces. Avoid crossing digital and analog traces if possible, and only make perpendicular crossings when absolutely necessary.
12.2 Layout Example
Figure 62. Layout Example