ZHCS861B April 2012 – June 2015 PGA450-Q1
PRODUCTION DATA.
| MIN | MAX | UNIT | ||
|---|---|---|---|---|
| Power-supply voltage | VPWR | –0.3 | 40 | V |
| Voltage | VREG, VPROG_OTP pin | –0.3 | 10 | V |
| LIN | –27 | 40 | V | |
| RBIAS, CIN, IN | –0.3 | 3 | V | |
| DVDD, XIN, XOUT | –0.3 | 2 | V | |
| OUTA, OUTB | –0.3 | 40 | V | |
| LIM | –1.5 | 1.5 | V | |
| Voltage on all other pins, VMAX | –0.3 | 6 | V | |
| Low-side FET current, IFET | 1.5 | A | ||
| Maximum operating junction temperature, TJmax | –40 | 150 | ℃ | |
| Storage temperature, Tstg | –40 | 125 | °C | |
| VALUE | UNIT | ||||
|---|---|---|---|---|---|
| V(ESD) | Electrostatic discharge | Human body model (HBM), per AEC Q100-002(1) | ±2000 | V | |
| IEC61000-4–2(2) | LIN pin | ±8000 | |||
| Charged device model (CDM), per AEC Q100-011 | Corner pins (1, 14, 15, and 28) | ±750 | |||
| Other pins | ±500 | ||||
| MIN | NOM | MAX | UNIT | |||
|---|---|---|---|---|---|---|
| VPWR | Power-supply voltage | 7 | 18 | V | ||
| IPWR | Power-supply current | Power up, TA = 105°C | 50 | mA | ||
| Active mode(1) temperature sensor off, TA = 105°C, VPWR = 18 V | 15 | mA | ||||
| Quiet mode(1), TA = 105°C, VPWR = 18 V | 7.5 | mA | ||||
| IPWRAVG | Average power-supply current(1) | 10 | mA | |||
| TA | Operating ambient temperature | –40 | 105 | ℃ | ||
| CVREG | Capacitance on VREG pin | 10 | 470 | µF | ||
| CVPWR | Capacitance on VPWR pin(2) | 47 | 100 | µF | ||
| CESR | ESR of capacitor on VREG pin | 2 | Ω | |||
| THERMAL METRIC(1) | PGA450-Q1 | UNIT | |
|---|---|---|---|
| PWP (TSSOP) | |||
| 28 PINS | |||
| RθJA | Junction-to-ambient thermal resistance | 68.7 | °C/W |
| RθJC | Junction-to-case (top) thermal resistance | 11.6 | °C/W |
| RθJB | Junction-to-board thermal resistance | 27.6 | °C/W |
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
|---|---|---|---|---|---|---|---|
| POWER SUPPLY | |||||||
| VPWRPOR | VPWR voltage for POR to occur | POR is deasserted | 3 | 4.2 | V | ||
| VAVDD | AVDD pin voltage | IAVDD = 5 mA | 4.75 | 5 | 5.25 | V | |
| IAVDD | AVDD pin load current | 5 | mA | ||||
| VDVDD | DVDD pin voltage | 1.8 | V | ||||
| VREF | VREF pin voltage | 3 | V | ||||
| VREG | |||||||
| VREGTOL | Transducer primary voltage tolerance | IREG = 100 µA | VPWR = 7 V VREG_SEL = 0_XXX for 4.7 V–5.4 V |
±100 | mV | ||
| VPWR = 10 V VREG_SEL = 1_XXX for 7.7 V–8.4 V |
±150 | ||||||
| VREGCHARGE | Transducer voltage droop while charging | IREG = 100 mA, below VREG_SEL setting | 500 | mV | |||
| VREGREADY | VREG_READY threshold | Below VREG_SEL setting | 250 | ||||
| IVREG | VREG output current | VPWR > VREG_SEL + 2.5 V | 90 | 100 | 110 | mA | |
| VPWR > VREG_SEL + 2 V | 100 | µA | |||||
| VREGI_S2G | VREG short-to-ground protection current | VPWR = 16 V, TA = 105 °C, no burst | 110 | mA | |||
| LOW-SIDE DRIVE MOSFETS | |||||||
| rds(on) | FET ON resistance | Iload = 500 mA, TA = 105 °C | 1.2 | Ω | |||
| IPULSE | Drain pulse current | 50 kHz | 1.5 | A | |||
| Drive clamping voltage | Vgs = 0 V, Idd = 10 mA | 40 | V | ||||
| Leakage current | 5 | µA | |||||
| LOW NOISE AMPLIFIER | |||||||
| AV | Gain | LNA_GAIN setting = 0b00 | 1680 | 1750 | 1820 | V/V | |
| LNA_GAIN setting = 0b01 | 892 | 930 | 968 | ||||
| LNA_GAIN Setting = 0b10 | 496 | 517 | 538 | ||||
| LNA_GAIN Setting = 0b11 | 99 | 104 | 109 | ||||
| RIN | Input impedance | 40 kHz | 100 | kΩ | |||
| Clamp voltage | –1.5 | 1.5 | V | ||||
| ILIM | Input current limit | 200 | mA | ||||
| Noise (input-referred of the signal chain) | IN pin = GND, TA = 105 °C, center frequency = 40 kHz, Bandwidth = 10 kHz | 0.7 | µVrms | ||||
| Input-referred PSRR | VPWR = 7 V, LNA gain setting = 0b00 | 93 | dB | ||||
| 12-BIT ADC | |||||||
| VADCREF | Input voltage range | 0 | 3 | V | |||
| DNL | 20% to 80% input range | 2.5 | LSB | ||||
| INL | 20% to 80% input range, best-fit curve | 4 | LSB | ||||
| Gain | Best-fit curve | 1373 | 1378 | 1383 | LSB/V | ||
| Offset | Best-fit curve | –15 | LSB | ||||
| 8-BIT DAC | |||||||
| VDAC_MAX | Output range | 0.133 | 1.125 | V | |||
| Gain | 3.9 | mV/Code | |||||
| Offset voltage | Output when DAC code is 000h at Rload = 100 kΩ to GND | 0.133 | V | ||||
| Full-scale voltage | Output when DAC code is 0xFF Rload = 100 kΩ to GND | 1.125 | V | ||||
| IDAC | Output current | DAC Code = 0x00 DAC Code = 0xFF, Rload = 100 kΩ |
12.5 | µA | |||
| INL | –2 | 2 | LSB | ||||
| DNL | –1 | 1 | LSB | ||||
| Capacitance load | 10 | pF | |||||
| TRANSDUCER SATURATION TIME | |||||||
| VSAT_TH | Saturation threshold | SAT_SEL = 200 mV | 200 | mV | |||
| SAT_SEL = 300 mV | 300 | mV | |||||
| SAT_SEL = 400 mV | 400 | mV | |||||
| SAT_SEL = 600 mV | 600 | mV | |||||
| TEMPERATURE SENSOR | |||||||
| Temperature sensor range | –40 | 140 | °C | ||||
| Temperature accuracy | –40°C to 105°C | –5 | 5 | °C | |||
| Temperature sensor code | 30°C | 0 | LSB | ||||
| Temperature sensor LSB | 1.75 | °C/LSB | |||||
| GPIOS, 8051 UART Tx AND Rx | |||||||
| VIH | GPIO input mode, high, Rx, | Rload > 10 kΩ | 3.5 | 5.3 | V | ||
| VIL | GPIO input mode, low, Rx | –0.3 | 1.5 | V | |||
| RPULLUP | Internal pullup on input | Pullup is to AVDD | 100 | KΩ | |||
| VOH | GPIO strong-mode output, high, Tx | IOH = 5 mA | 4 | V | |||
| VOL | GPIO strong-mode output, low, Tx | IOL = 5 mA | 0.8 | V | |||
| Total current on GPIO1 + GPIO2 +Tx pin | No load on AVDD pin | 5 | mA | ||||
| MEMORY | |||||||
| OTP programming voltage | 7.5 | 8 | 8.5 | V | |||
| OTP programming current | 2 | 5 | mA | ||||
| DIAGNOSTICS | |||||||
| VPWR_OV | VPWR overvoltage level | 25 | 28 | 32 | V | ||
| AVDD_UV | VPWR for AVDD undervoltage | 5.6 | V | ||||
| AVDD_OC | AVDD Overcurrent | 45 | 55 | 65 | mA | ||
| RBIAS_OC | RBIAS Overcurrent | 65 | 80 | 90 | µA | ||
| Low-side driver A/B drain monitor | 2.2 | 2.5 | 2.8 | V | |||
| Low-side driver A/B monitor | 2.2 | 2.5 | 2.8 | V | |||
| Over temperature shut-off protection | 150 | 200 | ℃ | ||||
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT |
|---|---|---|---|---|---|
| IBUS_LIM |
V BUS= 18 V |
40 | 200 | mA | |
| IBUS_PAS_dom | Driver off, VBUS= 0V, VPWR= 12 V | –1 | mA | ||
| IBUS_PAS_rec | Driver off, 7 V < VPWR < 18 V, 8 V < VBUS < 18 V, VBUS > VPWR | 20 | µA | ||
| IBUS_NO_GND | GNDDevice = V PWR, 0 < VBUS < 18 V, VPWR = 12 V | –1 | 1 | mA | |
| IBUS_NO_BAT | V PWR= GND, 0 < V BUS < 18 V | 100 | µA | ||
| VBUSdom | Receiver dominant state | 0.4 | VPWR | ||
| VBUSrec | Receiver recessive state | 0.6 | VPWR | ||
| VBUS_CNT | VBUS_CNT = (V th_dom+ V th_rec)/2 | 0.475 | 0.5 | 0.525 | VPWR |
| VHYS | VHYS = Vth_rec – Vth_dom | 0.175 | VPWR | ||
| RSlave | Serial resistor | 20 | 30 | 60 | KΩ |
| CIN | Input capacitance on LIN pin | 60 | pF |
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| High-level voltage (CS, SCK, SDI, SDO) | 3.5 | V | ||||
| Low-level voltage (CS, SCK, SDI, SDO) | 1.5 | V | ||||
| CL(SDO) | Capacitive load for data output (SDO) | 10 | pF | |||
| MIN | NOM | MAX | UNIT | ||
|---|---|---|---|---|---|
| D1 | THRec(max) = 0.744 × VPWR; THDom(max) = 0.581 × V PWR; V PWR= 7 V...18 V; tBit= 50 µs; D1 = tBus_rec(min)/ (2 × tBit) Load1; CBUS = 1 nF; RBUS = 1KΩ Load2; CBUS = 6.8 nF; RBUS = 660 Ω Load3: CBUS = 10 nF; RBUS = 500 Ω, see Figure 1. |
0.396 | |||
| D2 | THRec(min)= 0.522 × VPWR; THDom(min) = 0.284 × VPWR; VPWR= 7.6 V...18 V; tBit = 50 µs; D2 = tBus_rec(max)/ (2 × t Bit) Load1; CBUS = 1 nF; RBUS = 1 kΩ Load2; CBUS = 6.8 nF; R BUS = 660 Ω Load3; C BUS=10 nF; RBUS = 500 Ω, see Figure 1. |
0.581 | |||
| D3 | THRec(max) = 0.778 × VPWR; THDom(max) = 0.616 × V PWR; V PWR= 7 V to 18 V; tBit = 96 µs; D4 = tBus_rec(min) / (2 × t Bit) Load1; C BUS = 1 nF; RBUS = 1 kΩ Load2; CBUS = 6.8 nF; RBUS = 660 Ω Load3; CBUS = 10 nF; RBUS = 500 Ω, see Figure 1. |
0.417 | |||
| D4 | THRec(min) = 0.389 × VPWR; THDom(min) = 0.251 × VPWR; VPWR = 7.6 V to 18 V; tBit= 96 µs; D4 = tBus_rec(max) / (2 × t Bit) Load1; CBUS = 1 nF; RBUS = 1 kΩ Load2; CBUS = 6.8 nF; RBUS = 660 Ω Load3; CBUS = 10 nF; RBUS = 500 Ω, see Figure 1. |
0.590 | |||
| trx_pd | Propagation delay of receiver RRXD = 2.4 kΩ; CRXD = 20 pF |
6 | µs | ||
| trx_sym | Symmetry of receiver propagation delay rising edge with respect to falling edge RRXD = 2.4 kΩ; C RXD = 20 pF |
–2 | 2 | µs | |
| MIN | NOM | MAX | UNIT | |||
|---|---|---|---|---|---|---|
| fSCK | SPI frequency | 8 | MHz | |||
| tCSSCK | CS low to first SCK rising edge | See Figure 2. | 125 | ns | ||
| tSCKCS | Last SCK rising edge to CS rising edge | 125 | ns | |||
| tCSD | CS disable time | 375 | ns | |||
| tDS | SDI setup time | 25 | ns | |||
| tDH | SDI hold time | 25 | ns | |||
| tSDIS | SDI fall/rise time | 25 | ns | |||
| tSCKR | SCK rise time | 7 | ns | |||
| tSCKF | SCK fall time | 7 | ns | |||
| tSCKH | SCK high time | 62.5 | ns | |||
| tSCKL | SCK low time | 62.5 | ns | |||
| tSDO | SDO enable time | 25 | ns | |||
| tACCS | SCK rising edge to SDO data valid | 25 | ns | |||
| tSDOD | SDO disable time | 25 | ns | |||
| tSDOS | SDO rise/fall time | CSDO = 10 pF, see Figure 2. | 1 | 15 | ns | |
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| 12-BIT ADC | ||||||
| Conversion time | 1 | µs | ||||
| 8051W WARP CORE | ||||||
| FCORE_CLK | Core frequency | 16 | MHz | |||
| Memory interface | 1 | Wait State | ||||
| MEMORY | ||||||
| OTP programming time | 1 byte | 100 | µs | |||
| OTP data retention years | 105 °C | 10 | Years | |||
| EEPROM R/W cycles | 1000 | Cycles | ||||
| EEPROM data retention | 105 °C | 10 | Years | |||
| EEPROM programming time | 32 Bytes | 70 | ms | |||
| DIAGNOSTICS | ||||||
| Main oscillator underfrequency fault | 14 | MHz | ||||
| Main oscillator overfrequency fault | 18 | MHz | ||||
Figure 1. LIN Timing Diagram
Figure 2. SPI Clocking Details

| Input referred LNA AC noise in 10-kHz bandwidth around 40 kHz | ||
| Vnoise = 0.7 µVrms | ||

| BPF center frequency = 58 kHz | BPF bandwidth = 7 kHz | |


| BPF center frequency = 58 kHz | BPF bandwidth = 7 kHz | |