ZHCSL30B June 2009 – March 2020 PGA280
PRODUCTION DATA.
The PGA280 uses a 1-MHz internal oscillator, nominally. This clock can be brought out to pin GPIO6 if configured by the internal register setting to allow synchronization of external systems to this clock. If the PGA280 must be controlled by an external clock, GPIO06 can be configured as an oscillator input, thus overriding the internal oscillator. In order to maintain stable device performance, the frequency must be within the specified range shown in the Electrical Characteristics. The clock pulse duration is not critical, because this duration is internally divided down; however, less than 30% deviation is recommended. The GPIO6 input assumes a standard logic signal. Prevent overshoot at this pin, and provide approximately equal rise and fall times for the lowest influence on offset voltage as a result of coupled noise.
Expect a small amount of additional noise during the transition from the internal to external clock, or vice versa, for approximately eight clock periods because of phase mismatch.