SBASA14 May 2020 PCMD3180
PRODUCTION DATA.
- 1 Features
- 2 Applications
- 3 Description
- 4 Revision History
- 5 Pin Configuration and Functions
-
6 Specifications
- 6.1 Absolute Maximum Ratings
- 6.2 ESD Ratings
- 6.3 Recommended Operating Conditions
- 6.4 Thermal Information
- 6.5 Electrical Characteristics
- 6.6 Timing Requirements: I2C Interface
- 6.7 Switching Characteristics: I2C Interface
- 6.8 Timing Requirements: SPI Interface
- 6.9 Switching Characteristics: SPI Interface
- 6.10 Timing Requirements: TDM, I2S or LJ Interface
- 6.11 Switching Characteristics: TDM, I2S or LJ Interface
- 6.12 Timing Requirements: PDM Digital Microphone Interface
- 6.13 Switching Characteristics: PDM Digial Microphone Interface
- 6.14 Typical Characteristics
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3
Feature Description
- 7.3.1 Serial Interfaces
- 7.3.2 Phase-Locked Loop (PLL) and Clock Generation
- 7.3.3 Reference Voltage
- 7.3.4 Microphone Bias
- 7.3.5 Digital PDM Microphone Record Channel
- 7.3.6
Signal-Chain Processing
- 7.3.6.1 Programmable Digital Volume Control
- 7.3.6.2 Programmable Channel Gain Calibration
- 7.3.6.3 Programmable Channel Phase Calibration
- 7.3.6.4 Programmable Digital High-Pass Filter
- 7.3.6.5 Programmable Digital Biquad Filters
- 7.3.6.6 Programmable Channel Summer and Digital Mixer
- 7.3.6.7
Configurable Digital Decimation Filters
- 7.3.6.7.1
Linear Phase Filters
- 7.3.6.7.1.1 Sampling Rate: 8 kHz or 7.35 kHz
- 7.3.6.7.1.2 Sampling Rate: 16 kHz or 14.7 kHz
- 7.3.6.7.1.3 Sampling Rate: 24 kHz or 22.05 kHz
- 7.3.6.7.1.4 Sampling Rate: 32 kHz or 29.4 kHz
- 7.3.6.7.1.5 Sampling Rate: 48 kHz or 44.1 kHz
- 7.3.6.7.1.6 Sampling Rate: 96 kHz or 88.2 kHz
- 7.3.6.7.1.7 Sampling Rate: 192 kHz or 176.4 kHz
- 7.3.6.7.1.8 Sampling Rate: 384 kHz or 352.8 kHz
- 7.3.6.7.1.9 Sampling Rate 768 kHz or 705.6 kHz
- 7.3.6.7.2 Low-Latency Filters
- 7.3.6.7.3
Ultra-Low-Latency Filters
- 7.3.6.7.3.1 Sampling Rate: 16 kHz or 14.7 kHz
- 7.3.6.7.3.2 Sampling Rate: 24 kHz or 22.05 kHz
- 7.3.6.7.3.3 Sampling Rate: 32 kHz or 29.4 kHz
- 7.3.6.7.3.4 Sampling Rate: 48 kHz or 44.1 kHz
- 7.3.6.7.3.5 Sampling Rate: 96 kHz or 88.2 kHz
- 7.3.6.7.3.6 Sampling Rate 192 kHz or 176.4 kHz
- 7.3.6.7.3.7 Sampling Rate 384 kHz or 352.8 kHz
- 7.3.6.7.1
Linear Phase Filters
- 7.3.7 Interrupts, Status, and Digital I/O Pin Multiplexing
- 7.4 Device Functional Modes
- 7.5 Programming
- 7.6
Register Maps
- 7.6.1
Device Configuration Registers
- 7.6.1.1 Register Summary Table Page=0x00
- 7.6.1.2
Register Descriptions
- 7.6.1.2.1 PAGE_CFG Register (page = 0x00, address = 0x00) [reset = 0h]
- 7.6.1.2.2 SW_RESET Register (page = 0x00, address = 0x01) [reset = 0h]
- 7.6.1.2.3 SLEEP_CFG Register (page = 0x00, address = 0x02) [reset = 0h]
- 7.6.1.2.4 SHDN_CFG Register (page = 0x00, address = 0x05) [reset = 5h]
- 7.6.1.2.5 ASI_CFG0 Register (page = 0x00, address = 0x07) [reset = 30h]
- 7.6.1.2.6 ASI_CFG1 Register (page = 0x00, address = 0x08) [reset = 0h]
- 7.6.1.2.7 ASI_CFG2 Register (page = 0x00, address = 0x09) [reset = 0h]
- 7.6.1.2.8 ASI_CH1 Register (page = 0x00, address = 0x0B) [reset = 0h]
- 7.6.1.2.9 ASI_CH2 Register (page = 0x00, address = 0x0C) [reset = 1h]
- 7.6.1.2.10 ASI_CH3 Register (page = 0x00, address = 0x0D) [reset = 2h]
- 7.6.1.2.11 ASI_CH4 Register (page = 0x00, address = 0x0E) [reset = 3h]
- 7.6.1.2.12 ASI_CH5 Register (page = 0x00, address = 0x0F) [reset = 4h]
- 7.6.1.2.13 ASI_CH6 Register (page = 0x00, address = 0x10) [reset = 5h]
- 7.6.1.2.14 ASI_CH7 Register (page = 0x00, address = 0x11) [reset = 6h]
- 7.6.1.2.15 ASI_CH8 Register (page = 0x00, address = 0x12) [reset = 7h]
- 7.6.1.2.16 MST_CFG0 Register (page = 0x00, address = 0x13) [reset = 2h]
- 7.6.1.2.17 MST_CFG1 Register (page = 0x00, address = 0x14) [reset = 48h]
- 7.6.1.2.18 ASI_STS Register (page = 0x00, address = 0x15) [reset = FFh]
- 7.6.1.2.19 CLK_SRC Register (page = 0x00, address = 0x16) [reset = 10h]
- 7.6.1.2.20 PDMCLK_CFG Register (page = 0x00, address = 0x1F) [reset = 40h]
- 7.6.1.2.21 PDMIN_CFG Register (page = 0x00, address = 0x20) [reset = 0h]
- 7.6.1.2.22 GPIO_CFG0 Register (page = 0x00, address = 0x21) [reset = 22h]
- 7.6.1.2.23 GPO_CFG0 Register (page = 0x00, address = 0x22) [reset = 0h]
- 7.6.1.2.24 GPO_CFG1 Register (page = 0x00, address = 0x23) [reset = 0h]
- 7.6.1.2.25 GPO_CFG2 Register (page = 0x00, address = 0x24) [reset = 0h]
- 7.6.1.2.26 GPO_CFG3 Register (page = 0x00, address = 0x25) [reset = 0h]
- 7.6.1.2.27 GPO_VAL Register (page = 0x00, address = 0x29) [reset = 0h]
- 7.6.1.2.28 GPIO_MON Register (page = 0x00, address = 0x2A) [reset = 0h]
- 7.6.1.2.29 GPI_CFG0 Register (page = 0x00, address = 0x2B) [reset = 0h]
- 7.6.1.2.30 GPI_CFG1 Register (page = 0x00, address = 0x2C) [reset = 0h]
- 7.6.1.2.31 GPI_MON Register (page = 0x00, address = 0x2F) [reset = 0h]
- 7.6.1.2.32 INT_CFG Register (page = 0x00, address = 0x32) [reset = 0h]
- 7.6.1.2.33 INT_MASK0 Register (page = 0x00, address = 0x33) [reset = FFh]
- 7.6.1.2.34 INT_LTCH0 Register (page = 0x00, address = 0x36) [reset = 0h]
- 7.6.1.2.35 BIAS_CFG Register (page = 0x00, address = 0x3B) [reset = 0h]
- 7.6.1.2.36 CH1_CFG0 Register (page = 0x00, address = 0x3C) [reset = 0h]
- 7.6.1.2.37 CH1_CFG2 Register (page = 0x00, address = 0x3E) [reset = C9h]
- 7.6.1.2.38 CH1_CFG3 Register (page = 0x00, address = 0x3F) [reset = 80h]
- 7.6.1.2.39 CH1_CFG4 Register (page = 0x00, address = 0x40) [reset = 0h]
- 7.6.1.2.40 CH2_CFG0 Register (page = 0x00, address = 0x41) [reset = 0h]
- 7.6.1.2.41 CH2_CFG2 Register (page = 0x00, address = 0x43) [reset = C9h]
- 7.6.1.2.42 CH2_CFG3 Register (page = 0x00, address = 0x44) [reset = 80h]
- 7.6.1.2.43 CH2_CFG4 Register (page = 0x00, address = 0x45) [reset = 0h]
- 7.6.1.2.44 CH3_CFG0 Register (page = 0x00, address = 0x46) [reset = 0h]
- 7.6.1.2.45 CH3_CFG2 Register (page = 0x00, address = 0x48) [reset = C9h]
- 7.6.1.2.46 CH3_CFG3 Register (page = 0x00, address = 0x49) [reset = 80h]
- 7.6.1.2.47 CH3_CFG4 Register (page = 0x00, address = 0x4A) [reset = 0h]
- 7.6.1.2.48 CH4_CFG0 Register (page = 0x00, address = 0x4B) [reset = 0h]
- 7.6.1.2.49 CH4_CFG2 Register (page = 0x00, address = 0x4D) [reset = C9h]
- 7.6.1.2.50 CH4_CFG3 Register (page = 0x00, address = 0x4E) [reset = 80h]
- 7.6.1.2.51 CH4_CFG4 Register (page = 0x00, address = 0x4F) [reset = 0h]
- 7.6.1.2.52 CH5_CFG0 Register (page = 0x00, address = 0x50) [reset = 0h]
- 7.6.1.2.53 CH5_CFG2 Register (page = 0x00, address = 0x52) [reset = C9h]
- 7.6.1.2.54 CH5_CFG3 Register (page = 0x00, address = 0x53) [reset = 80h]
- 7.6.1.2.55 CH5_CFG4 Register (page = 0x00, address = 0x54) [reset = 0h]
- 7.6.1.2.56 CH6_CFG0 Register (page = 0x00, address = 0x55) [reset = 0h]
- 7.6.1.2.57 CH6_CFG2 Register (page = 0x00, address = 0x57) [reset = C9h]
- 7.6.1.2.58 CH6_CFG3 Register (page = 0x00, address = 0x58) [reset = 80h]
- 7.6.1.2.59 CH6_CFG4 Register (page = 0x00, address = 0x59) [reset = 0h]
- 7.6.1.2.60 CH7_CFG0 Register (page = 0x00, address = 0x5A) [reset = 0h]
- 7.6.1.2.61 CH7_CFG2 Register (page = 0x00, address = 0x5C) [reset = C9h]
- 7.6.1.2.62 CH7_CFG3 Register (page = 0x00, address = 0x5D) [reset = 80h]
- 7.6.1.2.63 CH7_CFG4 Register (page = 0x00, address = 0x5E) [reset = 0h]
- 7.6.1.2.64 CH8_CFG0 Register (page = 0x00, address = 0x5F) [reset = 0h]
- 7.6.1.2.65 CH8_CFG2 Register (page = 0x00, address = 0x61) [reset = C9h]
- 7.6.1.2.66 CH8_CFG3 Register (page = 0x00, address = 0x62) [reset = 80h]
- 7.6.1.2.67 CH8_CFG4 Register (page = 0x00, address = 0x63) [reset = 0h]
- 7.6.1.2.68 DSP_CFG0 Register (page = 0x00, address = 0x6B) [reset = 1h]
- 7.6.1.2.69 DSP_CFG1 Register (page = 0x00, address = 0x6C) [reset = 40h]
- 7.6.1.2.70 IN_CH_EN Register (page = 0x00, address = 0x73) [reset = F0h]
- 7.6.1.2.71 ASI_OUT_CH_EN Register (page = 0x00, address = 0x74) [reset = 0h]
- 7.6.1.2.72 PWR_CFG Register (page = 0x00, address = 0x75) [reset = 0h]
- 7.6.1.2.73 DEV_STS0 Register (page = 0x00, address = 0x76) [reset = 0h]
- 7.6.1.2.74 DEV_STS1 Register (page = 0x00, address = 0x77) [reset = 80h]
- 7.6.1.2.75 I2C_CKSUM Register (page = 0x00, address = 0x7E) [reset = 0h]
- 7.6.2 Programmable Coefficient Registers
- 7.6.1
Device Configuration Registers
- 8 Application and Implementation
- 9 Power Supply Recommendations
- 10Layout
- 11Device and Documentation Support
- 12Mechanical, Packaging, and Orderable Information
封裝選項(xiàng)
機(jī)械數(shù)據(jù) (封裝 | 引腳)
- RTW|24
散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)
- RTW|24
訂購(gòu)信息
7.3.1.2.2 Inter IC Sound (I2S) Interface
The standard I2S protocol is defined for only two channels: left and right. The device extends the same protocol timing for multichannel operation. In I2S mode, the MSB of the left slot 0 is transmitted on the falling edge of BCLK in the second cycle after the falling edge of FSYNC. Immediately after the left slot 0 data transmission, the remaining left slot data are transmitted in order. The MSB of the right slot 0 is transmitted on the falling edge of BCLK in the second cycle after the rising edge of FSYNC. Immediately after the right slot 0 data transmission, the remaining right slot data are transmitted in order. FSYNC and each data bit is transmitted on the falling edge of BCLK. Figure 21 to Figure 24 illustrate the protocol timing for I2S operation with various configurations.
Figure 21. I2S Mode Standard Protocol Timing (TX_OFFSET = 0) 
Figure 22. I2S Protocol Timing (TX_OFFSET = 1) 
Figure 23. I2S Protocol Timing (No Idle BCLK Cycles, TX_OFFSET = 0) 
Figure 24. I2S Protocol Timing (TX_OFFSET = 0 and BCLK_POL = 1) For proper operation of the audio bus in I2S mode, the number of bit clocks per frame must be greater than or equal to the number of active output channels (including left and right slots) times the programmed word length of the output channel data. The device FSYNC low pulse must be a number of BCLK cycles wide that is greater than or equal to the number of active left slots times the data word length configured. Similarly, the FSYNC high pulse must be a number of BCLK cycles wide that is greater than or equal to the number of active right slots times the data word length configured.