SBASA14 May 2020 PCMD3180
PRODUCTION DATA.
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
|---|---|---|---|---|---|---|---|
| PERFORMANCE FOR PDM INPUT CONVERSION | |||||||
| SNR | Signal-to-noise ratio, A-weighted(1)(2)(3) | No signal, input generated using 5th order PDM modulator | 128 | dB | |||
| No signal, input generated using 4th order PDM modulator | 118 | ||||||
| DR | Dynamic range, A-weighted(2)(3) | –60-dB full-scale signal input, input generated using 5th order PDM modulator | 127 | dB | |||
| –60-dB full-scale signal input, input generated using 4th order PDM modulator | 117 | ||||||
| OTHER PARAMETERS | |||||||
| Digital volume control range | Programmable 0.5-dB steps | –100 | 27 | dB | |||
| PDMCLKx output rate | Programmable | 0.7056 | 6.144 | MHz | |||
| Output data sample rate | Programmable | 7.35 | 768 | kHz | |||
| Output data sample word length | Programmable | 16 | 32 | Bits | |||
| Digital high-pass filter cutoff frequency | First-order IIR filter with programmable coefficients, –3-dB point (default setting) | 12 | Hz | ||||
| MICBIAS voltage | MICBIAS programmed to VREF and VREF programmed to either 2.75 V, 2.5 V, or 1.375 V | VREF | V | ||||
| Bypass to AVDD with 20-mA load | AVDD – 0.2 | ||||||
| DIGITAL I/O | |||||||
| VIL | Low-level digital input logic voltage threshold | All digital pins except PDMDINx_GPIx, SDA and SCL, IOVDD 1.8-V operation | –0.3 | 0.35 × IOVDD | V | ||
| All digital pins except PDMDINx_GPIx, SDA and SCL, IOVDD 3.3-V operation | –0.3 | 0.8 | |||||
| VIH | High-level digital input logic voltage threshold | All digital pins except PDMDINx_GPIx, SDA and SCL, IOVDD 1.8-V operation | 0.65 × IOVDD | IOVDD + 0.3 | V | ||
| All digital pins except PDMDINx_GPIx, SDA and SCL, IOVDD 3.3-V operation | 2 | IOVDD + 0.3 | |||||
| VOL | Low-level digital output voltage | All digital pins except PDMCLKx_GPOx, SDA and SCL, IOL = –2 mA, IOVDD 1.8-V operation | 0.45 | V | |||
| All digital pins except PDMCLKx_GPOx, SDA and SCL, IOL = –2 mA, IOVDD 3.3-V operation | 0.4 | ||||||
| VOH | High-level digital output voltage | All digital pins except PDMCLKx_GPOx, SDA and SCL, IOH = 2 mA, IOVDD 1.8-V operation | IOVDD – 0.45 | V | |||
| All digital pins except PDMCLKx_GPOx, SDA and SCL, IOH = 2 mA, IOVDD 3.3-V operation | 2.4 | ||||||
| VIL(I2C) | Low-level digital input logic voltage threshold | SDA and SCL | –0.5 | 0.3 x IOVDD | V | ||
| VIH(I2C) | High-level digital input logic voltage threshold | SDA and SCL | 0.7 x IOVDD | IOVDD + 0.5 | V | ||
| VOL1(I2C) | Low-level digital output voltage | SDA, IOL(I2C) = –3 mA, IOVDD > 2 V | 0.4 | V | |||
| VOL2(I2C) | Low-level digital output voltage | SDA, IOL(I2C) = –2 mA, IOVDD ≤ 2 V | 0.2 x IOVDD | V | |||
| IOL(I2C) | Low-level digital output current | SDA, VOL(I2C) = 0.4 V, standard-mode or fast-mode | 3 | mA | |||
| SDA, VOL(I2C) = 0.4 V, fast-mode plus | 20 | ||||||
| VIL(SHDNZ) | Low-level digital input logic voltage threshold | SHDNZ pin, AVDD 1.8-V operation | –0.3 | 0.25 × IOVDD | V | ||
| SHDNZ pin, AVDD 3.3-V operation | –0.3 | 0.9 | V | ||||
| VIH(SHDNZ) | High-level digital input logic voltage threshold | SHDNZ pin, AVDD 1.8-V operation | 0.75 × IOVDD | IOVDD + 0.3 | V | ||
| SHDNZ pin, AVDD 3.3-V operation | 2.25 | IOVDD + 0.3 | V | ||||
| IIL | Input logic-low leakage for digital inputs | All digital pins except PDMDINx_GPIx pins, input = 0 V | –5 | 0.1 | 5 | µA | |
| IIH | Input logic-high leakage for digital inputs | All digital pins except PDMDINx_GPIx pins, input = IOVDD | –5 | 0.1 | 5 | µA | |
| VIL(GPIx) | Low-level digital input logic voltage threshold | All PDMDINx_GPIx digital pins, AVDD 1.8-V operation | –0.3 | 0.35 × AVDD | V | ||
| All PDMDINx_GPIx digital pins, AVDD 3.3-V operation | –0.3 | 0.8 | |||||
| VIH(GPIx) | High-level digital input logic voltage threshold | All PDMDINx_GPIx digital pins, AVDD 1.8-V operation | 0.65 × AVDD | AVDD + 0.3 | V | ||
| All PDMDINx_GPIx digital pins, AVDD 3.3-V operation | 2 | AVDD + 0.3 | |||||
| VOL(GPOx) | Low-level digital output voltage | All PDMCLKx_GPOx digital pins, IOL = –2 mA, AVDD 1.8-V operation | 0.45 | V | |||
| All PDMCLKx_GPOx digital pins, IOL = –2 mA, AVDD 3.3-V operation | 0.4 | ||||||
| VOH(GPOx) | High-level digital output voltage | All PDMCLKx_GPOx digital pins, IOH = 2 mA, AVDD 1.8-V operation | AVDD – 0.45 | V | |||
| All PDMCLKx_GPOx digital pins, IOH = 2 mA, AVDD 3.3-V operation | 2.4 | ||||||
| IIL(GPIx) | Input logic-high leakage for digital inputs | All PDMDINx_GPIx digital pins, input = 0 V | –5 | 0.1 | 5 | µA | |
| IIH(GPIx) | Input logic-high leakage for digital inputs | All PDMDINx_GPIx digital pins, input = AVDD | –5 | 0.1 | 5 | µA | |
| CIN | Input capacitance for digital inputs | All digital pins | 5 | pF | |||
| RPD | Pulldown resistance for digital I/O pins when asserted on | 20 | kΩ | ||||
| TYPICAL SUPPLY CURRENT CONSUMPTION | |||||||
| IAVDD | Current consumption in hardware shutdown mode | SHDNZ = 0, AVDD = 3.3 V | 1 | µA | |||
| IAVDD | SHDNZ = 0, AVDD = 1.8 V, external AREG supply (AREG shorted to AVDD) | 1 | |||||
| IIOVDD | SHDNZ = 0, all external clocks stopped, IOVDD = 3.3 V | 0.1 | |||||
| IIOVDD | SHDNZ = 0, all external clocks stopped, IOVDD = 1.8 V | 0.1 | |||||
| IAVDD | Current consumption in sleep mode (software shutdown mode) | All external clocks stopped, AVDD = 3.3 V | 5 | µA | |||
| IAVDD | All external clocks stopped, AVDD = 1.8 V, external AREG supply (AREG shorted to AVDD) | 5 | |||||
| IIOVDD | All external clocks stopped, IOVDD = 3.3 V | 0.1 | |||||
| IIOVDD | All external clocks stopped, IOVDD = 1.8 V | 0.1 | |||||
| IAVDD | Current consumption with 8-channel PDM input recording, fS = 48 kHz, PDMCLKx = 64 × fS, PLL on and BCLK = 256 × fS | AVDD = 3.3 V | 11.9 | mA | |||
| IAVDD | AVDD = 1.8 V, external AREG supply (AREG shorted to AVDD) | 11.3 | |||||
| IIOVDD | IOVDD = 3.3 V | 0.7 | |||||
| IIOVDD | IOVDD = 1.8 V | 0.4 | |||||
| IAVDD | Current consumption with 4-channel PDM input recording, fS = 16 kHz, PDMCLKx = 96 × fS, PLL on and BCLK = 256 × fS | AVDD = 3.3 V | 7.2 | mA | |||
| IAVDD | AVDD = 1.8 V, external AREG supply (AREG shorted to AVDD) | 6.5 | |||||
| IIOVDD | IOVDD = 3.3 V | 0.2 | |||||
| IIOVDD | IOVDD = 1.8 V | 0.1 | |||||