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ZHCSPD7A April 2022 – September 2022 PCMD3140-Q1

PRODUCTION DATA

封裝選項(xiàng)

機(jī)械數(shù)據(jù) (封裝 | 引腳)

RTE|20
- MPQF596

散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)

訂購(gòu)信息

6.5 Electrical Characteristics

at T_A = 25°C, AVDD = 3.3 V, IOVDD = 3.3 V, f_IN = 1-kHz sinusoidal signal, f_S = 48 kHz, PDMCLKx = 64 × f_S,32-bit audio data, BCLK = 256 × f_S, TDM slave mode, and PLL on (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
PERFORMANCE FOR PDM INPUT CONVERSION
SNR	Signal-to-noise ratio, A-weighted⁽¹⁾⁽²⁾⁽³⁾	No signal, input generated using 5^th-order PDM modulator		130		dB
SNR	Signal-to-noise ratio, A-weighted⁽¹⁾⁽²⁾⁽³⁾	No signal, input generated using 4^th-order PDM modulator		118		dB
DR	Dynamic range, A-weighted⁽²⁾⁽³⁾	–60-dB full-scale signal input, input generated using 5^th-order PDM modulator		127		dB
DR	Dynamic range, A-weighted⁽²⁾⁽³⁾	–60-dB full-scale signal input, input generated using 4^th-order PDM modulator		116		dB
OTHER PARAMETERS
	Digital volume control range	Programmable 0.5-dB steps	–100		27	dB
	Output data sample rate	Programmable	7.35		768	kHz
	Output data sample word length	Programmable	16		32	Bits
	Digital high-pass filter cutoff frequency	First-order IIR filter with programmable coefficients, –3-dB point (default setting)		12		Hz
MICROPHONE BIAS
	MICBIAS noise	BW = 20 Hz to 20 kHz, A-weighted, 1-μF capacitor between MICBIAS and AVSS		2.1		μV_RMS
	MICBIAS voltage	MICBIAS programmed to VREF and VREF programmed to either 2.75 V, 2.5 V, or 1.375 V		VREF		V
	MICBIAS voltage	MICBIAS programmed to VREF × 1.096 and VREF programmed to either 2.75 V, 2.5 V, or 1.375 V		VREF × 1.096		V
	MICBIAS voltage	Bypass to AVDD with 5-mA load		AVDD – 0.2		V
	MICBIAS current drive				5	mA
	MICBIAS load regulation	MICBIAS programmed to either VREF or VREF × 1.096, measured up to max load	0	0.6	1	%
	MICBIAS overcurrent protection threshold		6.1			mA
DIGITAL I/O
V_IL	Low-level digital input logic voltage threshold	All digital pins except PDMDIN1_GPI1, PDMDIN2_GPI2, SDA and SCL, IOVDD 1.8-V operation	–0.3		0.35 × IOVDD	V
V_IL	Low-level digital input logic voltage threshold	All digital pins except PDMDIN1_GPI1, PDMDIN2_GPI2, SDA and SCL, IOVDD 3.3-V operation	–0.3		0.8	V
V_IH	High-level digital input logic voltage threshold	All digital pins except PDMDIN1_GPI1, PDMDIN2_GPI2, SDA and SCL, IOVDD 1.8-V operation	0.65 × IOVDD		IOVDD + 0.3	V
V_IH	High-level digital input logic voltage threshold	All digital pins except PDMDIN1_GPI1, PDMDIN2_GPI2, SDA and SCL, IOVDD 3.3-V operation	2		IOVDD + 0.3	V
V_OL	Low-level digital output voltage	All digital pins except PDMCLK_GPO1, SDA and SCL, I_OL = –2 mA, IOVDD 1.8-V operation			0.45	V
V_OL	Low-level digital output voltage	All digital pins except PDMCLK_GPO1, SDA and SCL, I_OL = –2 mA, IOVDD 3.3-V operation			0.4	V
V_OH	High-level digital output voltage	All digital pins except PDMCLK_GPO1, SDA and SCL, I_OH = 2 mA, IOVDD 1.8-V operation	IOVDD – 0.45			V
V_OH	High-level digital output voltage	All digital pins except PDMCLK_GPO1, SDA and SCL, I_OH = 2 mA, IOVDD 3.3-V operation	2.4			V
V_IL(I2C)	Low-level digital input logic voltage threshold	SDA and SCL	–0.5		0.3 x IOVDD	V
V_IH(I2C)	High-level digital input logic voltage threshold	SDA and SCL	0.7 x IOVDD		IOVDD + 0.5	V
V_OL1(I2C)	Low-level digital output voltage	SDA, I_OL(I2C) = –3 mA, IOVDD > 2 V			0.4	V
V_OL2(I2C)	Low-level digital output voltage	SDA, I_OL(I2C) = –2 mA, IOVDD ≤ 2 V			0.2 x IOVDD	V
I_OL(I2C)	Low-level digital output current	SDA, V_OL(I2C) = 0.4 V, standard-mode or fast-mode	3			mA
I_OL(I2C)	Low-level digital output current	SDA, V_OL(I2C) = 0.4 V, fast-mode plus	20			mA
I_IH	Input logic-high leakage for digital inputs	All digital pins except PDMDIN1_GPI1, PDMDIN2_GPI2 pins, input = IOVDD	–5	0.1	5	μA
I_IL	Input logic-low leakage for digital inputs	All digital pins except PDMDIN1_GPI1, PDMDIN2_GPI2 pins, input = 0 V	–5	0.1	5	μA
V_IL(GPIx)	Low-level digital input logic voltage threshold	PDMDIN1_GPI1, PDMDIN2_GPI2 digital pins, AVDD 1.8-V operation	–0.3		0.35 × AVDD	V
V_IL(GPIx)	Low-level digital input logic voltage threshold	PDMDIN1_GPI1, PDMDIN2_GPI2 digital pins, AVDD 3.3-V operation	–0.3		0.8	V
V_IH(GPIx)	High-level digital input logic voltage threshold	PDMDIN1_GPI1, PDMDIN2_GPI2 digital pins, AVDD 1.8-V operation	0.65 × AVDD		AVDD + 0.3	V
V_IH(GPIx)	High-level digital input logic voltage threshold	PDMDIN1_GPI1, PDMDIN2_GPI2 digital pins, AVDD 3.3-V operation	2		AVDD + 0.3	V
V_OL(GPOx)	Low-level digital output voltage	PDMDIN1_GPI1, PDMDIN2_GPI2 digital pins, I_OL = –2 mA, AVDD 1.8-V operation			0.45	V
V_OL(GPOx)	Low-level digital output voltage	PDMDIN1_GPI1, PDMDIN2_GPI2 digital pins, I_OL = –2 mA, AVDD 3.3-V operation			0.4	V
V_OH(GPOx)	High-level digital output voltage	PDMDIN1_GPI1, PDMDIN2_GPI2 digital pins, I_OH = 2 mA, AVDD 1.8-V operation	AVDD – 0.45			V
V_OH(GPOx)	High-level digital output voltage	PDMDIN1_GPI1, PDMDIN2_GPI2 digital pins, I_OH = 2 mA, AVDD 3.3-V operation	2.4			V
I_IH(GPIx)	Input logic-high leakage for digital inputs	PDMDIN1_GPI1, PDMDIN2_GPI2 digital pins, input = AVDD	–5	0.1	5	μA
I_IL(GPIx)	Input logic-high leakage for digital inputs	PDMDIN1_GPI1, PDMDIN2_GPI2 digital pins, input = 0 V	–5	0.1	5	μA
C_IN	Input capacitance for digital inputs	All digital pins		5		pF
R_PD	Pulldown resistance for digital I/O pins when asserted on			20		kΩ
TYPICAL SUPPLY CURRENT CONSUMPTION
I_AVDD	Current consumption in sleep mode (software shutdown mode)	All external clocks stopped, AVDD = 3.3 V		5		μA
I_AVDD		All external clocks stopped, AVDD = 1.8 V, external AREG supply (AREG shorted to AVDD)		10
I_IOVDD		All external clocks stopped, IOVDD = 3.3 V		0.5
I_IOVDD		All external clocks stopped, IOVDD = 1.8 V		0.3
I_AVDD	Current consumption with 4-channel PDM input recording	AVDD = 3.3 V		9.1		mA
I_AVDD		AVDD = 1.8 V, external AREG supply (AREG shorted to AVDD)		8.1
I_IOVDD		IOVDD = 3.3 V		0.1
I_IOVDD		IOVDD = 1.8 V		0.05
I_AVDD	Current consumption with 4-channel PDM input recording, f_S = 16 kHz, PDMCLKx = 96 × f_S, PLL on and BCLK = 384 × f_S	AVDD = 3.3 V		7.3		mA
I_AVDD		AVDD = 1.8 V, external AREG supply (AREG shorted to AVDD)		6.3
I_IOVDD		IOVDD = 3.3 V		0.1
I_IOVDD		IOVDD = 1.8 V		0.05

(1) Ratio of output level with 1-kHz full-scale sine-wave input, to the output level with no signal, measured A-weighted over a 20-Hz to 20-kHz bandwidth using an audio analyzer.

(2) All performance measurements done with 20-kHz low-pass filter and, where noted, A-weighted filter. Failure to use such a filter may result in higher THD and lower SNR and dynamic range readings than shown in the Electrical Characteristics. The low-pass filter removes out-of-band noise, which, although not audible, may affect dynamic specification values.

(3) The device performance parameters, SNR, DR and THD+N, are mainly limited by single-bit PDM modulator generated data output. The THD+N peformance for single-bit PDM modulator output itself is generally not so good for signal above –10-dB full-scale.