Table 37. Power Supply Pin Descriptions

10.2.1 XSMT = 0

When the XSMT pin is pulled low, the incoming PCM data is attenuated to 0, closely followed by a hard analog mute. This process takes 150 sample times (t_s) + 0.2 ms.

Because this mute time is mainly dominated by the sampling frequency, systems sampling at 192 kHz will mute much faster than a 48-kHz system.

10.2.2 Clock Error Detect

When clock error is detected on the incoming data clock, the PCM5252 devices switch to an internal oscillator, and continue to the drive the output, while attenuating the data from the last known value. Once this process is complete, the PCM5252 outputs are hard muted to ground.

10.2.3 Planned Shutdown

These auto-muting processes can be manipulated by system designs to mute before power loss in the following ways:

1. Assert XSMT low 150 t_S + 0.2 ms before power is removed.
Figure 76. Assert XSMT
2. Stop I²S clocks (SCK, BCK, LRCK) 3 ms before powerdown as shown in Figure 77.
Figure 77. Stop I²C Clocks

10.2.4 Unplanned Shutdown

Many systems use a low-noise regulator to provide an AVDD 3.3-V supply for the DAC. The XSMT Pin can take advantage of such a feature to measure the pre-regulated output from the system SMPS to mute the output before the entire SMPS discharges. Figure 78 shows how to configure such a system to use the XSMT pin. The XSMT pin can also be used in parallel with a GPIO pin from the system microcontroller/DSP or power supply.

Figure 78. Using the XSMT Pin

10.4.1 Power-On Reset, DVDD 3.3-V Supply

The PCM5252 includes a power-on reset function, as shown in Figure 81. With V_DD > 2.8 V, the power-on reset function is enabled. After the initialization period, the PCM5252 is set to its default reset state. Analog output will begin ramping after valid data has been passing through the device for the given group delay given by the digital interpolation filter selected.

Figure 81. Power-On Reset Timing, DVDD = 3.3 V

10.4.2 Power-On Reset, DVDD 1.8-V Supply

The PCM5252 includes a power-on reset function, as shown in Figure 82. With AVDD greater than approximately 2.8 V, CPVDD greater than approximately 2.8 V, and DVDD greater than approximately 1.5 V, the power-on reset function is enabled. After the initialization period, the PCM5252 is set to its default reset state.

Figure 82. Power-On Reset Timing, DVDD = 1.8 V

10.5.1 Setting Digital Power Supplies and I/O Voltage Rails

The internal digital core of the PCM5252 devices run from a 1.8-V supply. This can be generated by the internal LDO, or by an external 1.8-V supply.

DVDD is used to set the I/O voltage, and to be used as the input to the onchip LDO that creates the 1.8 V required by the digital core.

For systems that require 3.3-V I/O support, but lower power consumption, DVDD should be connected to 3.3 V and LDOO can be connected to an external 1.8-V source. Doing so will disable the onchip LDO.

When setting I/O voltage to be 1.8 V, both DVDD and LDOO must be provided with an external 1.8-V supply.

10.5.2 Power Save Modes

The PCM5252 devices offer two power-save modes: standby and power-down.

When a clock error (SCK, BCK, and LRCK) or clock halt is detected, the PCM5252 device automatically enters standby mode. The DAC and line driver are also powered down. The device can also be placed in standby mode via software command.

When BCK and LRCK remain at a low level for more than 1 second, the PCM5252 device automatically enters powerdown mode. Power-down mode disables the negative charge pump and bias/reference circuit, in addition to those disabled in standby mode. The device can also be placed in power-down mode via software command.

The detection time of BCK and LRCK halt can be controlled by Page 0, Register 44, D(2:0).

When expected audio clocks (SCK, BCK, LRCK) are applied to the PCM5252 device, or if BCK and LRCK start correctly while SCK remains at ground level for 16 successive LRCK periods, the device starts its powerup sequence automatically.

10.5.3 Power Save Parameter Programming