8.4.1 Audio Serial Interface

The audio interface port is a 3-wire serial port with the signals LRCK, BCK, and DIN. BCK is the serial audio bit clock, used to clock the serial data present on DIN into the serial shift register of the audio interface. Serial data is clocked into the PCM5242 on the rising edge of BCK. LRCK is the serial audio left/right word clock. LRCK polarity for Left/Right is given by the format selected.

The PCM5242 requires the synchronization of LRCK and system clock, but does not need a specific phase relation between LRCK and system clock.

If the relationship between LRCK and system clock changes more than ±5 SCK, internal operation is initialized within one sample period and analog outputs are forced to the bipolar zero level until resynchronization between LRCK and system clock is completed.

If the relationship between LRCK and BCK are invalid more than 4 LRCK periods, internal operation is initialized within one sample period and analog outputs are forced to the bipolar zero level until resynchronization between LRCK and BCK is completed.

8.4.2 PCM Audio Data Formats

The PCM5242 supports industry-standard audio data formats, including standard I²S and left-justified. Data formats are selected via Register (Pg0Reg40). All formats require binary 2s-complement, MSB-first audio data; up to 32-bit audio data is accepted.

The PCM5242 also supports right-justified and TDM/DSP in software control mode. I²S, LJ, RJ, and TDM/DSP are selected using Register (Pg0Reg40). All formats require binary 2s complement, MSB-first audio data. Up to 32 bits are accepted. Default setting is I²S and 24 bit word length.

Figure 18. Left Justified Audio Data Format

I²S Data Format; L-channel = LOW, R-channel = HIGH

Figure 19. I²S Audio Data Format

The following data formats are only available in software mode.

Right Justified Data Format; L-channel = HIGH, R-channel = LOW

Figure 20. Right Justified Audio Data Format

TDM/DSP Data Format; L-channel = FIRST, R-channel = LAST with OFFSET = 0

Figure 21. TDM/DSP 1 Audio Data Format

TDM/DSP Data Format; L-channel = FIRST, R-channel = LAST with OFFSET = 1

Figure 22. TDM/DSP 2 Audio Data Format

TDM/DSP Data Format; L-channel = FIRST, R-channel = LAST with OFFSET = N

Figure 23. TDM/DSP 3 Audio Data Format

8.4.3 Zero Data Detect

The PCM5242 has a zero-detect function. When the device detects the continuous zero data for both left and right channels, or separate channels, Analog mutes are set to both OUTL and OUTR, or separate OUTL and OUTR. These are controlled by Page0, Register 65, D(2:1) as shown in Table 5.

Continuous Zero data cycles are counted by LRCK, and the threshold of decision for analog mute can be set by Page 0, Register 59, D(6:4) for L-ch, and D(2:0) for Rch as shown in Table 6. Default values are 0 for both channels.

In Hardware mode, the device uses default values.

8.6.1 PCM5242 Audio Processing Options

8.6.2 Interpolation Filter

The PCM5242 provides 4 types of interpolation filters, selectable by writing to Page 0, Register 43, D(4:0).

Additional RAM based Hybrid Flows can be implemented by selecting Program 31, and downloading instructions and coefficients to the device.

The PCM5242supports four sampling modes (single rate, dual rate, quad rate, and octal rate) which produce different oversampling rates (OSR) in the interpolation digital filter operation. These are shown in Table 8.

Figure 24. Normal x8 Interpolation Filter Frequency Response

Figure 26. Normal x8 Interpolation Filter Passband Ripple

Figure 25. Normal x8 Interpolation Filter Impulse Response

Figure 27. Normal x4 Interpolation Filter Frequency Response

Figure 29. Normal x4 Interpolation Filter Passband Ripple

Figure 28. Normal x4 Interpolation Filter Impulse Response

Figure 30. Normal x2 Interpolation Filter Frequency Response

Figure 32. Normal x2 Interpolation Filter Passband Ripple

Figure 31. Normal x2 Interpolation Filter Impulse Response

Figure 33. Low latency x8 Interpolation Filter Frequency Response

Figure 35. Low latency x8 Interpolation Filter Passband Ripple

Figure 34. Low latency x8 Interpolation Filter Impulse Response

Figure 36. Low latency x4 Interpolation Filter Frequency Response

Figure 38. Low latency x4 Interpolation Filter Passband Ripple

Figure 37. Low latency x4 Interpolation Filter Impulse Response

Figure 39. Low latency x2 Interpolation Filter Frequency Response

Figure 41. Low latency x2 Interpolation Filter Passband Ripple

Figure 40. Low latency x2 Interpolation Filter Impulse Response

Figure 42. Asymmetric FIR x8 Interpolation Filter Frequency Response, Single Rate

Figure 44. Asymmetric FIR x8 Interpolation Filter Passband Ripple, Single Rate

Figure 43. Asymmetric FIR x8 Interpolation Filter Impulse Response, Single Rate

Figure 45. Asymmetric FIR x4 Interpolation Filter Frequency Response, Dual Rate

Figure 47. Asymmetric x4 Interpolation Filter Passband Ripple, Dual Rate

Figure 46. Asymmetric FIR x4 Interpolation Filter Impulse Response, Dual Rate

Figure 48. Asymmetric FIR x2 Interpolation Filter Frequency Response, Quad Rate

Figure 50. Asymmetric x2 Interpolation Filter Passband Ripple, Quad Rate

Figure 49. Asymmetric FIR x2 Interpolation Filter Impulse Response, Quad Rate

Figure 51. High-Attentuation x8 Interpolation Filter Frequency Response, Single Rate

Figure 53. High-Attentuation x8 Interpolation Filter Passband Ripple, Single Rate

Figure 52. High-Attentuation x8 Interpolation Filter Impulse Response, Single Rate

Figure 54. High-Attentuation x4 Interpolation Filter Frequency Response, Dual Rate

Figure 56. High-Attentuation x4 Interpolation Filter Passband Ripple, Dual Rate

Figure 55. High-Attentuation x4 Interpolation Filter Impulse Response, Dual Rate

Figure 57. High-Attentuation x2 Interpolation Filter Frequency Response, Quad Rate

Figure 59. High-Attentuation x2 Interpolation Filter Passband Ripple, Quad Rate

Figure 58. High-Attentuation x2 Interpolation Filter Impulse Response, Quad Rate

8.6.3 Fixed Audio Processing Flow (Program 5)

The PCM5242 implements signal processing capabilities and interpolation filtering via processing blocks. These fixed processing blocks give users the choice of how much and what type of signal processing they may use and which interpolation filter is applied.

The signal processing blocks available are:

• Biquad filters
• Multiband DRC
• Mono mixer
• Stereo mixer
• Master volume

The addresses of the coefficients are fixed when selecting the fixed processing flow, however, if these components are used in the RAM source mode (Program 31) the registers for coefficients will change. Users can find more details in Purepath Studio.

8.6.3.1 Processing Blocks – Detailed Descriptions

Figure 60 shows the fixed processing flow.

Figure 60. Preset Process Flow

Figure 61 shows a screen capture of PurePath Studio.

Figure 61. PurePath Studio Screen Capture

8.6.3.2 Biquad Section

The transfer function of each of the biquad filters is given by

Equation 1.

Figure 62. Biquad Block

Table 21. Biquad Filter Coefficients

Filter	Channel	Coefficient	Register
BIQUAD (1) - 1 BIQUAD (2) - 1	Lch, Rch	N0	C10 (Pg 44, Reg 48,49,50,51)
		N1	C11 (Pg 44, Reg 52,53,54,55)
		N2	C12 (Pg 44, Reg 56,57,58,59)
		D1	C13 (Pg 44, Reg 60,61,62,63)
		D2	C14 (Pg 44, Reg 64,65,66,67)
BIQUAD (1) - 2 BIQUAD (2) - 2	Lch, Rch	N0	C15 (Pg 44, Reg 68,69,70,71)
		N1	C16 (Pg 44, Reg 72,73,74,75)
		N2	C17 (Pg 44, Reg 76,77,78,79)
		D1	C18 (Pg 44, Reg 80,81,82,83)
		D2	C19 (Pg 44, Reg 84,85,86,87)
BIQUAD (1) - 3 BIQUAD (2) - 3	Lch, Rch	N0	C20 (Pg 44, Reg 88,89,90,91)
		N1	C21 (Pg 44, Reg 92,93,94,95)
		N2	C22 (Pg 44, Reg 96,97,98,99)
		D1	C23 (Pg 44, Reg 100,101, 102, 103)
		D2	C24 (Pg 44, Reg 104, 105, 106, 107)
BIQUAD (1) - 4 BIQUAD (2) - 4	Lch, Rch	N0	C25 (Pg 44, Reg 108, 109, 110, 111)
		N1	C26 (Pg 44, Reg 112, 113, 114, 115)
		N2	C27 (Pg 44, Reg 116, 117, 118, 119)
		D1	C28 (Pg 44, Reg 120, 121, 122, 123)
		D2	C29 (Pg 44, Reg 124, 125, 126, 127)
BIQUAD (1) - 5 BIQUAD (2) - 5	Lch, Rch	N0	C30 (Pg 45, Reg 8, 9, 10, 11)
		N1	C31 (Pg 45, Reg 12, 13, 14, 15)
		N2	C32 (Pg 45, Reg 16, 17, 18, 19)
		D1	C33 (Pg 45, Reg 20, 21, 22, 23)
		D2	C34 (Pg 45, Reg 24, 25, 26, 27)
BIQUAD (1) - 6 BIQUAD (2) - 6	Lch, Rch	N0	C35 (Pg 45, Reg 28, 29, 30, 31)
		N1	C36 (Pg 45, Reg 32, 33, 34, 35)
		N2	C37 (Pg 45, Reg 36, 37, 38, 39)
		D1	C38 (Pg 45, Reg 40, 41, 42, 43)
		D2	C39 (Pg 45, Reg 44, 45, 46, 47)
BIQUAD (3) - 1 BIQUAD (4) - 1	Lch, Rch	N0	C40 (Pg 45, Reg 48, 49, 50, 51)
		N1	C41 (Pg 45, Reg 52, 53, 54, 55)
		N2	C42 (Pg 45, Reg 56, 57, 58, 59)
		D1	C43 (Pg 45, Reg 60, 61, 62, 63)
		D2	C44 (Pg 45, Reg 64, 65, 66, 67)
BIQUAD (3) - 2 BIQUAD (4) - 2	Lch, Rch	N0	C45 (Pg 45, Reg 68, 69, 70, 71)
		N1	C46 (Pg 45, Reg 72, 73, 74, 75)
		N2	C47 (Pg 45, Reg 76, 77, 78, 79)
		D1	C48 (Pg 45, Reg 80, 81, 82, 83)
		D2	C49 (Pg 45, Reg 84, 85, 86, 87)
BIQUAD (5) - 1 BIQUAD (6) - 1	Lch, Rch	N0	C50 (Pg 45, Reg 88, 89, 90, 91)
		N1	C51 (Pg 45, Reg 92, 93, 94, 95)
		N2	C52 (Pg 45, Reg 96, 97, 98, 99)
		D1	C53 (Pg 45, Reg 100, 101, 102, 103)
		D2	C54 (Pg 45, Reg 104, 105, 106, 107)
BIQUAD (5) - 2 BIQUAD (6) - 2	Lch, Rch	N0	C55 (Pg 45, Reg 108, 109, 110, 111)
		N1	C56 (Pg 45, Reg 112, 113, 114, 115)
		N2	C57 (Pg 45, Reg 116, 117, 118, 119)
		D1	C58 (Pg 45, Reg 120, 121, 122, 123)
		D2	C59 (Pg 45, Reg 124, 125, 126, 127)
BIQUAD (7) - 1 BIQUAD (8) - 1	Lch, Rch	N0	C60 (Pg 46, Reg 8, 9, 10, 11)
		N1	C61 (Pg 46, Reg 12, 13, 14, 15)
		N2	C62 (Pg 46, Reg 16, 17, 18, 19)
		D1	C63 (Pg 46, Reg 20, 21, 22, 23)
		D2	C64 (Pg 46, Reg 24, 25, 26, 27)
BIQUAD (7) - 2 BIQUAD (8) - 2	Lch, Rch	N0	C65 (Pg 46, Reg 28, 29, 30, 31)
		N1	C66 (Pg 46, Reg 32, 33, 34, 35)
		N2	C67 (Pg 46, Reg 36, 37, 38, 39)
		D1	C68 (Pg 46, Reg 40, 41, 42, 43)
		D2	C69 (Pg 46, Reg 44, 45, 46, 47)

8.6.3.4 Stereo Mixer

Three stereo inputs are mixed into one stereo output with input signal gain given by Equation 2.

Equation 2.

where

• i=1:2,3

Figure 63 and Table 23 show the strereo mixer operation.

Figure 63. Stereo Mixer Block

Table 23. Stereo Mixer Coefficients

Coefficient	Register	Description
Stereo_Mixer_1_MixGain1	C148 (Pg 48, Reg 120, 121, 122, 123)
Stereo_Mixer_1_MixGain2	C149 (Pg 48, Reg 124, 125, 126, 127)
Stereo_Mixer_1_MixGain3	C150 (Pg 49, Reg 8, 9, 10, 11)

8.6.3.5 Stereo Multiplexer

The Stereo Multiplexer selects one or 2 from 4 stereo input channels.

Figure 64. Stereo Multiplexer Block

Table 24. Stereo Multiplexer Select Coefficient

Coefficient	Register	Description
Stereo_Mux_1_MuxSelect	C152 (Pg 49, Reg 16, 17, 18, 19)

Table 25. Stereo Multiplexer Input Coefficient

Coefficient	Register	Description
C_to_D_1_Coefval C_to_D_2_Coefval	C153 (Pg 49, Reg 20, 21, 22, 23)

8.6.3.6 Mono Mixer

The Mono Mixer computes a weighted sum of 2 input channels and produces an output.

Figure 65. Mono Mixer Block

Table 26. Mono Mixer Coefficients

Coefficient	Register	Description
Mono_Mixer_1_MixGain1	C154 (Pg 49, Reg 24, 25, 26, 27)
Mono_Mixer_1_MixGain2	C155 (Pg 49, Reg 28, 29, 30, 31)

8.7.1 Analog Outputs

The PCM5242 devices include a two-channel DAC, with differential outputs. Each pin has a full-scale output voltage is 2.1V_rms with ground center output. This equates to a 4.2V_rms differential output. A dc-coupled load is supported in addition to an ac-coupled load, if the load resistance conforms to the specification. The PCM5242 DAC outputs on the OUTLP, OUTLN, OUTRP, and OUTRN terminals have market-leading low out-of-band noise, which offer up to 20dB lower out-of-band noise compared with existing DAC technology.

Many applications require an external low-pass RC filter (470Ω + 1.2nF) to provide sufficient out-of-band noise rejection. This RC filter provides the added advantage of improved protection against ESD damage.

The PCM5242 can also support single ended outputs, using OUTLP and OUTRP respectively. A single 470Ω and 2.2nF capacitor can be used on each pin in single ended mode.

The choice between VREF and VCOM modes affects the maximum output level. This is explained in Voltage Reference and Output Levels.

Figure 66. Optional Low Pass Filters

8.7.2 Choosing Between VREF and VCOM Modes

VREF mode is the default configuration. This mode allows full 2.1V_rms signal output. As shown in Recommended Operating Conditions, the minimum AVDD to avoid clipping is 3.2V.

VCOM mode allows setting a custom common-mode voltage when required by the application. This somewhat limits the output signal swing before clipping.

8.7.3 Digital Volume Control

A basic digital volume control with range from 24 dB to -103 dB and mute is available on each channels by Page 0, Resister 61, D(7:0) for L-ch and Register 62, D(7:0) for R-ch. These volume controls all have 0.5 dB step programmability over most gain and attenuation ranges. Table 29 lists the detailed gain versus programmed setting for this basic volume control. Volume can be changed for both L-ch and R-ch at the same time or independently by Page 0, Register 60, D(1:0). When D(1:0) set 00 (default), independent control is selected. When D(1:0) set 01, R-ch accords with L-ch volume. When D(1:0) set 10, L-ch accords with R-ch volume. To set D(1:0) to 11 is prohibited.

Ramp-up frequency and ramp-down frequency can be controlled by Page 0, Register 63, D(7:6) and D(3:2) as shown in Table 30. Also Ramp-up step and ramp-down step can be controlled by Page 0, Register 63 D(5:4) and D(1:0) as shown in Table 31.

8.7.4 Analog Gain Control

Analog gain control can be selected between 2V_rms FS (0dB) or 1V_rms FS (-6dB). Gain is controlled via hardware by the AGNS pin, and via software (SPI/I²C), Page 1, Register 2, D4(L-ch) / D0(R-ch).

8.8.1 Clocking Overview

The PCM5242 devices have flexible systems for clocking. Internally, the device requires a number of clocks, mostly at related clock rates to function correctly. All of these clocks can be derived from the Serial Audio Interface in one form or another.

Figure 67. Audio flow with respective clocks

As shown in Figure 67 the basic data flow at basic sample rate (f_S). Once the data is brought into the serial audio interface, it gets processed, interpolated and modulated all the way to 128 × f_S before arriving at the current segments for the final digital to analog conversion.

The clock tree is shown in Figure 68.

Figure 68. PCM5242 Clock Distribution Tree

The Serial Audio Interface typically has 4 connections SCK (System Master Clock), BCK (Bit Clock), LRCK (Left Right Word Clock) and Data. The device has an internal PLL that is used to take either SCK or BCK and create the higher rate clocks required by the miniDSP and the DAC clock.

In situations where the highest audio performance is required, it’s suggested that the SCK is brought to the device, along with BCK and LRCK. The device should be configured so that the PLL is only providing a clock source to the miniDSP. By ensuring that the DACCK (DAC Clock) is being driven by the external SCK source, jitter evident in the PLL (in all PLL's) is kept out of the DAC, Charge Pump and Oversampling system.

Everything else should be a division of the incoming SCK. This is done by setting DAC CLK Source Mux (SDAC in the diagram above) to use SCK as a source, rather than the output of the SCK/PLL Mux. Code Examples for this are available in SLAC622

When the Auto Clock Configuration bit is set (Page0/ Register 0x25), no additional clocks configuration is required. However, when setting custom PLL values etc, the target output rates should match those shown in the recommended PLL values of Table 50.

8.8.2 Clock Slave Mode With Master Clock (SCK) Input (4 Wire I²S)

The PCM5242 requires a system clock to operate the digital interpolation filters and advanced segment DAC modulators. The system clock is applied at the SCK input and supports up to 50MHz. The PCM5242 system-clock detection circuit automatically senses the system-clock frequency. Common audio sampling frequencies in the bands of 8kHz, 16kHz, (32kHz - 44.1kHz - 48kHz), (88.2kHz - 96kHz), (176.4kHz -192kHz), and 384kHz with ±4% tolerance are supported. Values in the parenthises are "grouped" when detected, e.g. 88.2kHZ and 96kHz are detected as "double rate", 32kHz, 44.1kHz and 48kHz will be detected as "single rate".

In the presence of a valid bit SCK, BCK and LRCK in software mode, the device will autoconfigure the clock tree and PLL to drive the miniDSP as required.

The sampling frequency detector sets the clock for the digital filter, Delta Sigma Modulator (DSM) and the Negative Charge Pump (NCP) automatically. Table 32 shows examples of system clock frequencies for common audio sampling rates.

SCK rates that are not common to standard audio clocks, between 1MHz and 50MHz, are only supported in software mode by configuring various PLL and clock-divider registers. This programmability allows the device to become a clock master and drive the host serial port with LRCK and BCK, from a non-audio related clock (for example, using 12MHz to generate 44.1kHz (LRCK) and 2.8224MHz (BCK) ).

See Timing Requirements: PCM Audio Data for clock timing requirements.

8.8.3 Clock Slave Mode with BCK PLL to Generate Internal Clocks (3-Wire PCM)

The system clock PLL mode allows designers to use a simple 3-wire I²S audio source. The 3-wire source reduces the need for a high frequency SCK, making PCB layout easier, and reduces high frequency electromagnetic interference.

In hardwired mode, the internal PLL is disabled as soon as an external SCK is supplied.

In hardwired mode, the device starts up expecting an external SCK input, but if BCK and LRCK start correctly while SCK remains at ground level for 16 successive LRCK periods, then the internal PLL starts, automatically generating an internal SCK from the BCK reference. Specific BCK rates are required to generate an appropriate master clock.Table 33 describes the minimum and maximum BCK per LRCK for the integrated PLL to automatically generate an internal SCK.

In software mode, the user must set all the PLL registers and clock divider registers for referencing BCK. See Clock Generation Using The PLL for more information. Recommended values can be found in Table 50.

8.8.4 Clock Generation Using The PLL

The PCM5242 supports a wide range of options to generate the required clocks for the DAC section as well as interface and other control blocks as shown in Figure 68.

The clocks for the PLL require a source reference clock. This clock is sourced as the incoming BCK or SCK. In software mode, a GPIO can also be used.

The source reference clock for the PLL reference clock is selected by programming the SRCREF value on Page 0, Register 13, D(6:4). The PCM5242 provides several programmable clock dividers to achieve a variety of sampling rates for the DAC and clocks for the NCP, OSR, and the miniDSP. OSRCK for OSR must be set at 16f_S frequency by DOSR on Page0, Register 30, D(6:0). See Figure 68.

If PLL functionality is not required, set the PLLEN value on Page 0, Register 4, D(0) to 0. In this situation, an external SCK is required.

8.8.5 PLL Calculation

The PCM5242 has an on-chip PLL with fractional multiplication to generate the clock frequency needed by the audio DAC, Negative Charge Pump, Modulator and Digital Signal Processing blocks. The programmability of the PLL allows operation from a wide variety of clocks that may be available in the system. The PLL input (PLLCKIN) supports clock frequencies from 1MHz to 50MHz and is register programmable to enable generation of required sampling rates with fine precision.

The PLL is enabled by default. The PLL can be turned on by writing to Page 0, Register 4, D(0). When the PLL is enabled, the PLL output clock PLLCK is given by Equation 3:

Equation 3.

R = 1, 2, 3,4, ... , 15, 16

J = 4,5,6, . . . 63, and D = 0000, 0001, 0002, . . . 9999

K = [J value].[D value]

P = 1, 2, 3, ... 15

R, J, D, and P are programmable. J is the integer portion of K (the numbers to the left of the decimal point), while D is the fractional portion of K (the numbers to the right of the decimal point, assuming four digits of precision).

8.8.6 Clock Master Mode from Audio Rate Master Clock

In Master Mode, the device generates bit clock (BCK) and left-right clock (LRCK) and outputs them on the appropriate pins. To configure the device in this mode, first put the device into reset, then use registers BCKO and LRKO (Pg 0, Reg 9 0x09). Then reset the LRCK and BCK divider counters using bits RBCK and RLRK (Pg 0, Reg 12 0x0C). Finally exit reset.

An example of this is given in Register Programming Examples SLAC622.

Figure 69 shows a simplified serial port clock tree for the device in master mode.

Figure 69. Simplified clock tree for SCK sourced master mode

In master mode, SCK is an input and BCK/LRCK are outputs. BCK and LRCK are integer divisions of SCK. Master mode with a non-audio rate master clock source will require external GPIO’s to use the PLL in standalone mode.

The PLL will also need to be configured to ensure that the onchip miniDSP processor can be driven at its maximum clock rate.

Register changes that need to be done include switching the device into master mode, and setting the divider ratio.

Here is an example of using 24.576MCLK as a master clock source and driving the BCK and LRCK with integer dividers to create 48kHz.

In this mode, the DAC section of the device is also running from the PLL output. While the PLL inside the PCM5242 is one that has been spec’d well enough to achieve the stated performance, using the SCK CMOS Oscillator source will have less jitter.

To switch the DAC clocks (SDAC in the Figure 68) the following registers should be modified

• Clock Tree Flex Mode ( Page 253, Registers 0x3F and 0x40)
• DAC & OSR Source Clock Register (Page 0, Reg 14) – set to 0x30 (SCK input, and OSR is set to whatever the DAC source is)
• The DAC clock divider should be 16FS.
  • 16*48kHz = 768kHz
  • 24.576MHz (SCK in) / 768kHz = 32
  • Therefor, divide ratio for register DDAC (Page 0, Reg 28 0x1C) should be set to 32. The may the register is mapped gives 0x00 = 1, so 32 must be converter to 0x1F (31dec).

An example configuration can be found in SLAC622

8.8.7 Clock Master from a Non-Audio Rate Master Clock

The classic example here is running 12MHz Master clock for a 48kHz sampling system. Given the clock tree for the device (shown in Figure 68), a non-audio clock rate cannot be brought into the SCK to the PLL in master mode. Therefore, the PLL source must be configured to be a GPIO pin, and the output brought back into another GPIO pin.

Figure 70. Application diagram for using non-audio clock sources to generate audio clocks

The clock flow through the system is shown above. The newly generated SCK must be brought out of the device on a GPIO pin, then brought into the SCK pin for integer division to create BCK and LRCK outputs.

A code example for configuring this mode is provided in SLAC622

8.9.1 Choosing A Control Mode

SPI Mode is selected by connecting MODE1 to DVDD. SPI mode uses four signal lines and allows higher-speed full-duplex communication between the host and the PCM5242.

I²C Mode is selected by connecting MODE1 to DGND and Mode2 to DVDD. I²C uses two signal lines for half-duplex communication, and is widely used in a variety of devices.

Hardware Control Mode is selected by connecting both MODE1 and MODE2 pins to DGND. Hardware control is useful in applications that do not require on-the-fly device-reconfiguration changes in operating features such as gain or filter latency selection.

See Pin Assignments for a comparison of pin assignments for the 32-terminal QFN.

8.9.1.1 Software Control

8.9.1.1.1 SPI Interface

The SPI interface is a 4-wire synchronous serial port which operates asynchronously to the serial audio interface and the system clock (SCK). The serial control interface is used to program and read the on-chip mode registers.

The control interface includes MISO (pin 24), MOSI (pin 11), MC (pin 12), and MS (pin 18). MISO (Master In Slave Out) is the serial data output, used to read back the values of the mode registers; MOSI (Master Out Slave In) is the serial data input, used to program the mode registers.

MC is the serial bit clock, used to shift data in and out of the control port by falling edge of MC, and MS is the mode control enable with LOW active, used to enable the internal mode register access. If feedback from the device is not required, the MISO pin can be assigned to GPIO1 by register control.

8.9.1.1.1.1 Register Read/Write Operation

All read/write operations for the serial control port use 16-bit data words. Figure 71 shows the control data word format. The most significant bit is the read/write bit. For write operations, the bit must be set to 0. For read operations, the bit must be set to 1. There are seven bits, labeled IDX[6:0], that hold the register index (or address) for the read and write operations. The least significant eight bits, D[7:0], contain the data to be written to, or the data that was read from, the register specified by IDX[6:0].

Figure 71 and Figure 72 show the functional timing diagram to write or read through the serial control port. MS is held at a logic-1 state until a register access. To start the register write or read cycle, set MS to logic 0. Sixteen clocks are then provided on MC, corresponding to the 16 bits of the control data word on MOSI and read-back data on MISO. After the eighth clock cycle has completed, the data from the indexed-mode control register appears on MISO during the read operation. After the sixteenth clock cycle has completed, the data is latched into the indexed-mode control register during the write operation. To write or read subsequent data, MS is set to logic 1 once (See t_MHH in Figure 76).

Figure 71. Control Data Word Format; MDI

NOTE

B8 is used for selection of “Write” or “Read”. Setting = 0 indicates a “Write”, while = 1 indicates a ”Read”. Bits 15–9 are used for register address. Bits 7–0 are used for register data. Multiple-byte write or read (up to 8 bytes) is supported while MS is kept low. The address field becomes the initial address, automatically incrementing for each byte.

Figure 72. Serial Control Format; Write, Single Byte

Figure 73. Serial Control Format; Write, Multiple Byte

Figure 74. Serial Control Format; Read

Figure 75. Serial Control Format; Read, Multiple Byte

Figure 76. Control Interface Timing

Table 37. Control Interface Timing

	Parameters	Min	Max	Units
tMCY	MC Pulse Cycle Time	100		ns
tMCL	MC Low Level Time	40
tMCH	MC High Level Time	40
tMHH	MS High Level Time	20
tMSS	MS ↓ Edge to MC ↑ Edge	30
tMSH	MS Hold Time(1)	30
tMDH	MDI Hold Time	15
tMDS	MDI Set-up Time	15
tMOS	MC Rise Edge to MDO Stable		20

(1) MC falling edge for LSB to MS rising edge.

8.9.1.1.2 I²C Interface

The PCM5242 supports the I²C serial bus and the data transmission protocol for standard and fast mode as a slave device.

In I²C mode, the control terminals are changed as follows.

Table 38. I²C Pins and Functions

Signal	Pin	I/O	Description
SDA	11	I/O	I2C data
SCL	12	I	I2C clock
ADR2	16	I	I2C address 2
ADR1	24	I	I2C address 1

8.9.1.1.2.1 Slave Address

Table 39. I²C Slave Address

MSB							LSB
1	0	0	1	1	ADR2	ADR1	R/ W

The PCM5242 has 7 bits for its own slave address. The first five bits (MSBs) of the slave address are factory preset to 10011 (0x9x). The next two bits of the address byte are the device select bits which can be user-defined by the ADR1 and ADR0 terminals. A maximum of four devices can be connected on the same bus at one time. This gives a range of 0x98, 0x9A, 0x9C and 0x9E. Each PCM5242 responds when it receives its own slave address.

8.9.1.1.2.2 Register Address Auto-Increment Mode

Figure 77. Auto Increment Mode

Auto-increment mode allows multiple sequential register locations to be written to or read back in a single operation, and is especially useful for block write and read operations.

8.9.1.1.2.3 Packet Protocol

A master device must control packet protocol, which consists of start condition, slave address, read/write bit, data if write or acknowledge if read, and stop condition. The PCM5242 supports only slave receivers and slave transmitters.

Figure 78. Packet Protocol

Table 40. Write Operation - Basic I²C Framework

Transmitter	M	M	M	S	M	S	M	S		S	M
Data Type	St	slave address	R/	ACK	DATA	ACK	DATA	ACK		ACK	Sp

Table 41. Read Operation - Basic I²C Framework

Transmitter	M	M	M	S	S	M	S	M		M	M
Data Type	St	slave address	R/	ACK	DATA	ACK	DATA	ACK		NACK	Sp

M = Master Device; S = Slave Device; St = Start Condition Sp = Stop Condition

8.9.1.1.2.4 Write Register

A master can write to any PCM5242 registers using single or multiple accesses. The master sends a PCM5242 slave address with a write bit, a register address with auto-increment bit, and the data. If auto-increment is enabled, the address is that of the starting register, followed by the data to be transferred. When the data is received properly, the index register is incremented by 1 automatically. When the index register reaches 0x7F, the next value is 0x0. Table 42 shows the write operation.

Table 42. Write Operation

Transmitter

M

M

M

S

M

S

M

S

M

S

S

M

Data Type

St

slave addr

W

ACK

inc

reg addr

ACK

write data 1

ACK

write data 2

ACK

ACK

Sp

M = Master Device; S = Slave Device; St = Start Condition Sp = Stop Condition; W = Write; ACK = Acknowledge

8.9.1.1.2.5 Read Register

A master can read the PCM5242 register. The value of the register address is stored in an indirect index register in advance. The master sends a PCM5242 slave address with a read bit after storing the register address. Then the PCM5242 transfers the data which the index register points to. When auto-increment is enabled, the index register is incremented by 1 automatically. When the index register reaches 0x7F, the next value is 0x0. Table 43 shows the read operation.

Table 43. Read Operation

Transmitter

M

M

M

S

M

S

M

M

M

S

S

M

M

M

Data Type

St

slave addr

W

ACK

inc

reg addr

ACK

Sr

slave addr

R

ACK

data

ACK

NACK

Sp

M = Master Device; S = Slave Device; St = Start Condition; Sr = Repeated start condition; Sp = Stop Condition; W = Write; R = Read; NACK = Not acknowledge

8.9.1.1.2.6 Timing Characteristics

Figure 79. Register Access Timing

Table 44. I²C Bus Timing

SYMBOL	PARAMETER	CONDITIONS	MIN	MAX	UNIT
fSCL	SCL clock frequency	Standard		100	kHz
		Fast		400	kHz
tBUF	Bus free time between a STOP and START condition	Standard	4.7		µs
		Fast	1.3
tLOW	Low period of the SCL clock	Standard	4.7		µs
		Fast	1.3
tHI	High period of the SCL clock	Standard	4.0		µs
		Fast	600		ns
tRS-SU	Setup time for (repeated)START condition	Standard	4.7		µs
		Fast	600		ns
tS-HD	Hold time for (repeated)START condition	Standard	4.0		µs
tRS-HD		Fast	600		ns
tD-SU	Data setup time	Standard	250		ns
		Fast	100
tD-HD	Data hold time	Standard	0	900	ns
		Fast	0	900
tSCL-R	Rise time of SCL signal	Standard	20 + 0.1CB	1000	ns
		Fast	20 + 0.1CB	300
tSCL-R1	Rise time of SCL signal after a repeated START condition and after an acknowledge bit	Standard	20 + 0.1CB	1000	ns
		Fast	20 + 0.1CB	300
tSCL-F	Fall time of SCL signal	Standard	20 + 0.1CB	1000	ns
		Fast	20 + 0.1CB	300
tSDA-R	Rise time of SDA signal	Standard	20 + 0.1CB	1000	ns
		Fast	20 + 0.1CB	300
tSDA-F	Fall time of SDA signal	Standard	20 + 0.1CB	1000	ns
		Fast	20 + 0.1CB	300
tP-SU	Setup time for STOP condition	Standard	4.0		µs
		Fast	600		ns
CB	Capacitive load for SDA and SCL line			400	pF
tSP	Pulse width of spike suppressed	Fast		50	ns
VNH	Noise margin at High level for each connected device (including hysteresis)		0.2VDD		V

8.9.2 Choosing Between VREF and VCOM Modes

See Choosing Between VREF and VCOM Modes for information on configuring these modes.