ZHCS234B August 2012 – January 2016 PCM5141 , PCM5142
PRODUCTION DATA.
- 1 特性
- 2 應用
- 3 說明
- 4 修訂歷史記錄
- 5 Device Comparison
- 6 Pin Configuration and Functions
-
7 Specifications
- 7.1 Absolute Maximum Ratings
- 7.2 ESD Ratings
- 7.3 Recommended Operating Conditions
- 7.4 Thermal Information
- 7.5 Electrical Characteristics
- 7.6 Timing Requirements: SCK Input
- 7.7 Timing Requirements: PCM Audio Data
- 7.8 Timing Requirements: I2S Master
- 7.9 Timing Requirements: XSMT
- 7.10 Switching Characteristics
- 7.11 Typical Characteristics
-
8 Detailed Description
- 8.1 Overview
- 8.2 Functional Block Diagram
- 8.3
Feature Description
- 8.3.1 Terminology
- 8.3.2 Audio Data Interface
- 8.3.3 XSMT Pin (Soft Mute / Soft Un-Mute)
- 8.3.4 Audio Processing
- 8.3.5 DAC Outputs
- 8.3.6
Reset and System Clock Functions
- 8.3.6.1 Clocking Overview
- 8.3.6.2 Clock Slave Mode With Master and System Clock (SCK) Input (4 Wire I2S)
- 8.3.6.3 Clock Slave Mode With BCK PLL to Generate Internal Clocks (3-Wire PCM)
- 8.3.6.4 Clock Generation Using the PLL
- 8.3.6.5 PLL Calculation
- 8.3.6.6 Clock Master Mode from Audio Rate Master Clock
- 8.3.6.7 Clock Master from a Non-Audio Rate Master Clock
- 8.4 Device Functional Modes
- 8.5 Programming
- 9 Application and Implementation
- 10Power Supply Recommendations
- 11Layout
- 12Register Maps
- 13器件和文檔支持
- 14機械、封裝和可訂購信息
9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.
9.1 Application Information
The PCM514x family is flexible, and this flexibility gives rise to a number of design questions that define the design requirements for a given application.
9.2 Typical Application
Figure 77. Simplified Schematic, Hardware-Controlled Subsystem
9.2.1 Design Requirements
- Single-ended 2.1-VRMS analog outputs
- 3-wire I2S interface (BCK PLL)
- Single 3.3-V supply
9.2.2 Detailed Design Procedure
- Clock and PLL setup (See Reset and System Clock Functions.) Ensure incoming BCK meets minimum requirements.
- XSMT pin setup for 12-V monitoring (See External Power Sense Undervoltage Protection Mode.)
- Single-supply 3.3-V operation (See Setting Digital Power Supplies and I/O Voltage Rails.)
9.2.3 Application Curve
Figure 78. PCM5141A FFT Plot, DC to 20 kHz With a 1-kHz, –60-dBFS Input