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SLASE64A December 2014 – June 2017 PCM1860-Q1 , PCM1861-Q1 , PCM1862-Q1 , PCM1863-Q1 , PCM1864-Q1 , PCM1865-Q1

PRODUCTION DATA.

封裝選項

機械數據 (封裝 | 引腳)

DBT|30
- MPDS019J

散熱焊盤機械數據 (封裝 | 引腳)

訂購信息

11 Power Supply Recommendations

11.1 Power-Supply Distribution and Requirements

The PCM186x-Q1 powers the device using the pins shown in Figure 68.

PCM1860-Q1 PCM1861-Q1 PCM1862-Q1 PCM1863-Q1 PCM1864-Q1 PCM1865-Q1 pcm186x-power-tree.gif

Figure 68. PCM186x-Q1 Power Distribution Tree

The PCM186x-Q1 uses a combination of 3.3-V functional blocks and 1.8-V functional blocks to achieve high analog performance, combined with high levels of digital integration. As such, the device has three internal power rails. AVDD provides the analog circuits with a clean 3.3-V rail. DVDD is used for 3.3-V digital clock circuits. Externally, AVDD and DVDD can be connected together without significant impact to performance. The final rail, IOVDD, is used for driving the input/output digital circuitry.

The PCM186x-Q1 integrates an on-chip LDO to convert an external 3.3 V to the 1.8 V required by the digital core. The LDO input is derived from IOVDD. Power-supply pin descriptions are listed in Table 24.

Table 24. Power-Supply Pin Descriptions

NAME	DESCRIPTION
AVDD	Analog voltage supply (3.3 V) that powers the ADC, PGA, reference, and secondary ADC.
DVDD	Digital voltage supply (3.3 V) that is used for the PLL and the oscillator circuit.
IOVDD	Input/output pin voltage. Also used as a source for the internal LDO for the digital circuit.
LDO	Output from the on-chip LDO that is used with a 0.1-µF decoupling capacitor. Can be driven (used as power input) with a 1.8-V supply to bypass the on-chip LDO for lower power consumption.
AGND	Analog ground
DGND	Digital ground

11.2 1.8-V Support

All PCM186x-Q1 devices can support external devices with a 1.8 V I/O. This operating mode is configured by driving IOVDD and LDO with 1.8 V.

11.3 Brownout Conditions

The PCM186x-Q1 devices do not have a brownout detector, or a reset pin to hold while the system is powering up. Make sure that the system design meets minimum AVDD, DVDD and IOVDD requirements.

11.4 Power-Up Sequence

The power-up sequence consists of the following steps:

Power-on reset
1. Power up AVDD, DVDD and IOVDD
2. Check if LDO is being driven with an external 1.8 V, or is an output. Enable LDO if required.
3. Release digital reset
Wait until analog voltage reference is stable
Configure clock (PLL requires < 250 µs)
Fade-in audio ADC content

11.5 Lowest Power-Down Modes

To achieve the lowest levels of power down and sleep current, the following recommended write sequences are suggested on PCM186x-Q1 software-controlled devices:

11.5.1 Lowest Power In Standby Mode (AVDD = DVDD = IOVDD = 3.3 V)

Consumption as low as 0.59 mW

0x00=0x00 //select page0
0x70=0x14 //power down reference
0x00=0x03 //select page3
0x12=0x41 //disable OSC
0x00=0x00 //select page0

11.5.2 Lowest Power in Sleep or Energysense Mode (AVDD = DVDD = IOVDD = 3.3 V)

Consumption as low as 14 mW

Clocks must be running during this process

0x00=0x00 //select page0

0x70=0x72 //enter in sleep mode

0x00=0xfd //select page253

0x14=0x10 //change global bias current

0x00=0x00 //select page0

Now stop the clocks

11.5.3 Lower Power in Sleep or Energysense Mode (AVDD = DVDD 3.3 V and IOVDD = 1.8 V)

Consumption as low as 11.15 mW

Clocks must be running during this process

0x00=0x00 //select page0

0x70=0x72 //enter in sleep mode

0x00=0xfd //select page253

0x14=0x10 //change global bias current

0x00=0x00 //select page0

stop the clocks (note: make sure the clock IO is 1.8 V)

11.6 Power-On Reset Sequencing Timing Diagram

PCM1860-Q1 PCM1861-Q1 PCM1862-Q1 PCM1863-Q1 PCM1864-Q1 PCM1865-Q1 pcm186x_pwr_up-down.gif

Figure 69. Power-On Reset Timing Diagram

11.7 Power Connection Examples

11.7.1 3.3-V AVDD, DVDD, and IOVDD Example

This example shows the most typical usage. One single supply, shared between all three supply voltage inputs. Rail-connected decoupling capacitors are not shown. Figure 70 shows 3.3-V supply for all supplies. Figure 71 shows separate 3.3 V for AVDD and DVDD.

NOTE

There is no disadvantage in separating the AVDD and DVDD, as the device waits until both are present before powering up.

PCM1860-Q1 PCM1861-Q1 PCM1862-Q1 PCM1863-Q1 PCM1864-Q1 PCM1865-Q1 pcm186x_typ_pwr3v3.gif

Figure 70. 3.3 V for All Supplies

PCM1860-Q1 PCM1861-Q1 PCM1862-Q1 PCM1863-Q1 PCM1864-Q1 PCM1865-Q1 pcm186x_pwr_separate_a_dvdd.gif

Figure 71. Separate 3.3 V for AVDD and DVDD

11.7.2 3.3-V AVDD, DVDD With 1.8-V IOVDD Example for Lower-Power Applications

The PCM186x-Q1 also supports interfacing to lower power 1.8-V processors, as shown in Figure 72. In the presence of an external 1.8 V connected to LDO, the internal LDO that takes DVDD (3.3 V) and converts it to the 1.8-V core voltage is bypassed. Under such conditions, IOVDD will then be used as the 1.8-V source for the digital core of the device. In such systems, it is still important to have 3.3 V for DVDD, as specific sections of the digital core in the device run from 3.3 V.

PCM1860-Q1 PCM1861-Q1 PCM1862-Q1 PCM1863-Q1 PCM1864-Q1 PCM1865-Q1 pcm186x_pwr_separate_iovdd.gif

Figure 72. 1.8-V IOVDD With 3.3 V for AVDD and DVDD

11.8 Fade In

This sequence is the final stage of the power up and is illustrated in Figure 73. After the PLL has locked, the ADC starts running, and the data follows the fade-in sequence according to the following steps:

Detect a zero crossing audio input.
Increment the volume towards 0 dB with S-shaped volume.
Repeat from step 1 until the result is 0 dB. The number of steps from mute to 0 dB is 48 steps.
If zero crossing does not occur for 8192 sample times (= time out), change the volume-per-sample time.

PCM1860-Q1 PCM1861-Q1 PCM1862-Q1 PCM1863-Q1 PCM1864-Q1 PCM1865-Q1 pcm186x_zerocrossingfadein.gif

Figure 73. S-Curve Fade-In Behavior