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SLASE64A December 2014 – June 2017 PCM1860-Q1 , PCM1861-Q1 , PCM1862-Q1 , PCM1863-Q1 , PCM1864-Q1 , PCM1865-Q1

PRODUCTION DATA.

封裝選項

機械數據 (封裝 | 引腳)

DBT|30
- MPDS019J

散熱焊盤機械數據 (封裝 | 引腳)

訂購信息

7 Specifications

7.1 Absolute Maximum Ratings

over operating temperature (unless otherwise noted)⁽¹⁾

		MIN	MAX	UNIT
Supply voltage	AVDD to AGND	–0.3	3.9	V
	DVDD to DGND	–0.3	3.9
	IOVDD to DGND	–0.3	3.9
Ground voltage differences	AGND to DGND	–0.3	0.3	V
Digital input voltage	Digital input to DGND	–0.3	IOVDD + 0.3	V
Digital input voltage	XI to DGND	–0.3	2.1	V
Analog input voltage	VINxx to AGND	–1.7	5.0	V
Temperature	Operating ambient, T_A	–40	125	°C
	Junction, T_J	–40	150
	Storage, T_stg	–40	150

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7.2 ESD Ratings

				VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per AEC Q100-002⁽¹⁾		±2000	V
V_(ESD)	Electrostatic discharge	Charged-device model (CDM), per AEC Q100-011		±750	V

(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

7.3 Recommended Operating Conditions

			MIN	NOM	MAX	UNIT
POWER
AVDD	Analog supply voltage to AGND		3.0	3.3	3.6	V
DVDD	Digital supply voltage to DGND		3.0	3.3	3.6	V
IOVDD	IO supply voltage to DGND	at 1.8 V	1.62	1.8	1.98	V
IOVDD	IO supply voltage to DGND	at 3.3 V	3.0	3.3	3.6	V
LDO	LDO pin voltage to DGND (LDO is an input when using external 1.8-V power supply)		IOVDD – 0.3	IOVDD	IOVDD + 0.3	V
TEMPERATURE
T_A	Operating ambient temperature		–40		125	°C

7.4 Thermal Information

THERMAL METRIC⁽¹⁾		PCM186x-Q1	UNIT
		DBT (TSSOP)
		30 PINS
R_θJA	Junction-to-ambient thermal resistance	79.6	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	15.1	°C/W
R_θJB	Junction-to-board thermal resistance	33.1	°C/W
ψ_JT	Junction-to-top characterization parameter	0.4	°C/W
ψ_JB	Junction-to-board characterization parameter	32.6	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

7.5 Electrical Characteristics: PGA and ADC AC Performance

all specifications at T_A = 25°C, AVDD = 3.3 V, DVDD = 3.3 V, IOVDD = 3.3 V, master mode, single-speed mode, f_S = 48 kHz, system clock = 256 × f_S, and 24-bit data (unless otherwise noted)

PARAMETER		TEST CONDITIONS		MIN	TYP	MAX	UNIT
PRIMARY PGA AND ADC
	Input channel signal-to-noise ratio, differential input	0-dB PGA gain, –60-dB input signal, master mode at Diff input	PCM1860-Q1 PCM1862-Q1 PCM1864-Q1	97	103		dB
			PCM1861-Q1 PCM1863-Q1 PCM1865-Q1	97	110		dB
		32-dB PGA gain⁽¹⁾, –86-dB input signal, master mode at Diff input		85	90		dB
	Input channel THD+N, differential input	0-dB PGA gain, –1-dB input signal, master mode at Diff input		–85	–93		dB
	Input channel THD+N, differential input	32-dB PGA gain, –33-dB input signal, master mode at Diff input		–76	–84		dB
	L channel to R channel separation line input	0-dB PGA gain, –1-dB input signal, master mode			–105		dB
	L channel to R channel separation mic input	20-dB PGA gain, –1-dB input signal, master mode			–105		dB
	L1 channel to L2 channel separation line input	0-dB PGA gain, –1-dB input signal, master mode			–105		dB
	R1 channel to R2 channel separation line input	0-dB PGA gain, –1-dB input signal, master mode			–105		dB
	L1 channel to L2 channel separation mic input	20-dB PGA gain, –1-dB input signal, master mode			–105		dB
	R1 channel to R2 channel separation mic input	20-dB PGA gain, –1-dB input signal, master mode			–105		dB
	Range of analog PGA	–12 to +12 dB (1-dB step), 20 dB, and 32 dB		–12⁽²⁾		32	dB
	Accuracy of PGA + ADC				0.5		dB
	Matching between PGA + ADCs on-chip				0.05		dB
	Full-scale voltage input	Single-ended mode				2.1	V_RMS
	Full-scale voltage input	Differential mode (2.1 V_RMS per pin)				4.2	V_RMS
	Input channel signal-to-noise ratio, single-ended input	0-dB PGA gain, –60-dB input signal, master mode at SE input	PCM1860-Q1 PCM1862-Q1 PCM1864-Q1		103		dB
		0-dB PGA gain, –60-dB input signal, master mode at SE input	PCM1861-Q1 PCM1863-Q1 PCM1865-Q1		106		dB
		32-dB PGA gain, –92-dB input signal, master mode at SE input			75		dB
	Input channel THD+N, single-ended input	0-dB PGA gain, –1-dB input signal, master mode at SE input			87		dB
	Input channel THD+N, single-ended input	32-dB PGA gain, –33-dB input signal, master mode at SE input			68		dB
	Input impedance per analog input pin	PCM1864-Q1 and PCM1865-Q1			10		kΩ
	Input impedance per analog input pin	PCM1860-Q1, PCM1861-Q1, PCM1862-Q1, and PCM1863-Q1			20		kΩ
CMRR	Common-mode rejection ratio	Differential input, 1-kHz signal on both pins and measure level at output			56		dB
SECONDARY ADC PERFORMANCE
	Default Energysense signal detection threshold	At 1 kHz			–57		dBFS
	Energysense signal bandwidth				10		kHz
	Energysense accuracy⁽²⁾				3		dB
	Secondary ADC accuracy				12		bits
	Secondary ADC sampling rate			8		192	kHz

(1) 32-dB gain when using differential mode inputs is only available in SW-controlled devices.

(2) Specified by design.

7.6 Electrical Characteristics: DC

all specifications at T_A = 25°C, AVDD = 3.3 V, DVDD = 3.3 V, IOVDD = 3.3 V, slave mode, single-speed mode, f_S = 48 kHz, system clock = 512 × f_S, and 24-bit data (unless otherwise noted)

PARAMETER		TEST CONDITIONS	TYP	MAX	UNIT
POWER
	AVDD current	2-channel device, AVDD = DVDD = IOVDD = 3.3 V, active mode	18		mA
	DVDD current		0.01		mA
	IOVDD current		6.2		mA
	Total Power		80		mW
	AVDD current	2-channel device, AVDD = DVDD = IOVDD = 3.3 V, sleep mode	2.8		mA
	DVDD current		0.353		mA
	IOVDD current		2.2		mA
	Total power		17.6		mW
	AVDD current	2-channel device, AVDD = DVDD = IOVDD = 3.3 V, standby mode for software device	0.06		mA
	DVDD current		0.015		mA
	IOVDD current		0.12		mA
	Total power		0.64		mW
	AVDD current	2-channel device, AVDD = DVDD = IOVDD = 3.3 V, standby mode for hardware device	1.3		mA
	DVDD current		0.353		mA
	IOVDD current		1.6		mA
	Total power		10.725		mW
	AVDD current	2-channel device, AVDD = DVDD = 3.3 V, IOVDD = LDO = 1.8 V, active mode	18		mA
	DVDD current		0.015		mA
	IOVDD and LDO Current		5.4		mA
	Total power		69.2		mW
	AVDD current	2-channel device, AVDD = DVDD = 3.3 V IOVDD = LDO = 1.8 V, sleep mode	2.8		mA
	DVDD current		0.353		mA
	IOVDD and LDO Current		2		mA
	Total power		13.995		mW
	AVDD current	2-channel device, AVDD = DVDD = 3.3 V, IOVDD = LDO = 1.8 V, standby mode for software device	0.06		mA
	DVDD current		0.007		mA
	Total power⁽¹⁾		0.221		mW
	AVDD current	2-channel device, AVDD = DVDD = 3.3 V, IOVDD = LDO = 1.8 V, standby mode for hardware device	1.3		mA
	DVDD current		0.35		mA
	IOVDD and LDO Current		1.4		mA
	Total power		7.965		mW
	AVDD current	4-channel device, AVDD = DVDD = IOVDD = 3.3 V, active mode	31		mA
	DVDD current		0.01		mA
	IOVDD current		10		mA
	Total power		135.3		mW
	AVDD current	4-channel device, AVDD = DVDD = IOVDD = 3.3 V, sleep mode	2.8		mA
	DVDD current		0.35		mA
	IOVDD current		2.2		mA
	Total power		17.655		mW
	AVDD current	4-channel device, AVDD = DVDD = IOVDD = 3.3 V, standby mode for software device	0.06		mA
	DVDD current		0.015		mA
	IOVDD current		0.12		mA
	Total power		0.644		mW
	AVDD current	4-channel device, AVDD = DVDD = IOVDD = 3.3 V, standby mode for hardware device	1.3		mA
	DVDD current		0.35		mA
	IOVDD current		0.16		mA
	Total power		10.725		mW
	AVDD current	4-channel device, AVDD = DVDD = 3.3 V, IOVDD = LDO = 1.8 V, active mode	31		mA
	DVDD current		0.01		mA
	IOVDD and LDO Current		8.3		mA
	Total power		117.3		mW
	AVDD current	4-channel device, AVDD = DVDD = 3.3 V, IOVDD = LDO = 1.8 V, sleep mode	2.8		mA
	DVDD current		0.35		mA
	IOVDD and LDO Current		2		mA
	Total power		13.995		mW
	AVDD current	4-channel device, AVDD = DVDD = 3.3 V, IOVDD = LDO = 1.8 V, standby mode for software device	0.06		mA
	DVDD current		0.007		mA
	Total power⁽¹⁾		0.221		mW
	AVDD current	4-channel device, AVDD = DVDD = 3.3 V, IOVDD = LDO = 1.8 V, standby mode for hardware device	1.3		mA
	DVDD current		0.35		mA
	IOVDD and LDO Current		1.4		mA
	Total power		7.965		mW
	Additional current consumption	on IOVDD when XTAL is used	0.5		mA
		on DVDD in BCK PLL mode	1.5		mA
		on IOVDD when master mode is enabled	2		mA
		IOVDD = 3.3 V or IOVDD = LDO = 1.8 V, f_S = 192 kHz, 2-channel active mode	4		mA
		IOVDD = 3.3 V or IOVDD = LDO = 1.8 V, f_S = 192 kHz, 4-channel active mode	7.5		mA
PSRR	Power-supply rejection ratio		80		dB
MIC BIAS
	Mic bias noise		5		µV_RMS
	Mic bias current drive		4		mA
	Mic bias voltage		2.6		V
DIGITAL I/O
V_OH	Output logic high voltage level	I_OH = 2 mA	75		%IOVDD
V_OL	Output logic low voltage level	I_OL = –2 mA	25		%IOVDD
\|I_IH\|1	Input logic high current level	All digital pins		10	µA
\|I_IL\|1	Input logic low current level	All digital pins		–10	µA

(1) IOVDD and LDO current consumption is negligible for software-controlled devices in standby mode.

7.7 Electrical Characteristics: Digital Filter

all specifications at T_A = 25°C, AVDD = 3.3 V, DVDD = 3.3 V, IOVDD = 3.3 V, master mode, single-speed mode, f_S = 48 kHz, system clock = 256 × f_S, and 24-bit data (unless otherwise noted)

PARAMETER		TYP	UNIT
CLASSIC FIR
	Pass band	0.454	f_S
	Stop band	0.583	f_S
	Pass-band ripple	±0.05	dB
	Stop-band attenuation	–65	dB
	Group delay or latency	30	Samples
	HPF –3-dB cutoff frequency	1	Hz
LOW LATENCY IIR
	Pass band	0.454	f_S
	Stop band	0.546	f_S
	Pass-band ripple	±0.02	dB
	Stop-band attenuation	–75	dB
	Group delay or latency	10	Samples
	HPF –3-dB cutoff frequency	1	Hz

7.8 Timing Requirements: External Clock

all specifications at T_A = 25°C, AVDD = 3.3 V, DVDD = 3.3 V, IOVDD = 3.3 V, master mode, single-speed mode, f_S = 48 kHz, system clock = 256 × f_S, 24-bit data (unless otherwise noted)

		MIN	MAX	UNIT
XTAL support		15	35	MHz
MCLK frequency	3.3 V on MCLK pin	1	50	MHz
MCLK	1.8 V MCLK input on XI pin	1	50	MHz
MCLK input duty cycle	1.8 V MCLK	48%	52%
Maximum BCK frequency	IOVDD = 3.3 V		50	MHz
Maximum BCK frequency	IOVDD = 1.8 V		25	MHz

7.9 Timing Requirements: I²C Control Interface

		CONDITIONS	MIN	MAX	UNIT
f_SCL	SCL clock frequency	Standard		100	kHz
f_SCL	SCL clock frequency	Fast		400	kHz
t_BUF	Bus free time between a STOP and START condition	Standard	4.7		µs
t_BUF	Bus free time between a STOP and START condition	Fast	1.3		µs
t_LOW	Low period of the SCL clock	Standard	4.7		µs
t_LOW	Low period of the SCL clock	Fast	1.3		µs
t_HI	High period of the SCL clock	Standard	4.0		µs
t_HI	High period of the SCL clock	Fast	600		ns
t_RS-SU	Setup time for repeated START condition	Standard	4.7		µs
t_RS-SU	Setup time for repeated START condition	Fast	600		ns
t_S-HD	Hold time for START condition	Standard	4.0		µs
t_S-HD	Hold time for START condition	Fast	600		ns
t_RS-HD	Hold time for repeated START condition	Standard	4.0		µs
t_RS-HD	Hold time for repeated START condition	Fast	600		ns
t_D-SU	Data setup time	Standard	250		ns
t_D-SU	Data setup time	Fast	100		ns
t_D-HD	Data hold time	Standard	0	900	ns
t_D-HD	Data hold time	Fast	0	900	ns
t_SCL-R	Rise time of SCL signal	Standard	20 + 0.1C_B	1000	ns
t_SCL-R	Rise time of SCL signal	Fast	20 + 0.1C_B	300	ns
t_SCL-R1	Rise time of SCL signal after a repeated START condition and after an acknowledge bit	Standard	20 + 0.1C_B	1000	ns
t_SCL-R1		Fast	20 + 0.1C_B	300	ns
t_SCL-F	Fall time of SCL signal	Standard	20 + 0.1C_B	1000	ns
t_SCL-F	Fall time of SCL signal	Fast	20 + 0.1C_B	300	ns
t_SDA-R	Rise time of SDA signal	Standard	20 + 0.1C_B	1000	ns
t_SDA-R	Rise time of SDA signal	Fast	20 + 0.1C_B	300	ns
t_SDA-F	Fall time of SDA signal	Standard	20 + 0.1C_B	1000	ns
t_SDA-F	Fall time of SDA signal	Fast	20 + 0.1C_B	300	ns
t_P-SU	Setup time for STOP condition	Standard	4.0		µs
t_P-SU	Setup time for STOP condition	Fast	600		ns
C_B	Capacitive load for SDA and SCL line			400	pF
t_SP	Pulse duration of spike suppressed	Fast		50	ns
V_NH	Noise margin at high level for each connected device (including hysteresis)		0.2V_DD		V

PCM1860-Q1 PCM1861-Q1 PCM1862-Q1 PCM1863-Q1 PCM1864-Q1 PCM1865-Q1 tim_def_I2C_bus_las831.gif

Figure 1. I²C Control Interface Timing

7.10 Timing Requirements: SPI Control Interface

		MIN	MAX	UNIT
t_MCY	MC pulse period	100		ns
t_MCL	Pulse duration, MC low	40		ns
t_MCH	Pulse duration, MC high	40		ns
t_MHH	Pulse duration, MS high	20		ns
t_MSS	MS falling edge to MC rising edge	30		ns
t_MSH	MS hold time⁽¹⁾	30		ns
t_MDH	MOSI hold time	15		ns
t_MDS	MOSI setup time	15		ns
t_MOS	MC rising edge to MDO stable		20	ns

(1) MC falling edge for LSB to MS rising edge.

PCM1860-Q1 PCM1861-Q1 PCM1862-Q1 PCM1863-Q1 PCM1864-Q1 PCM1865-Q1 cont_if_tim_las831.gif

Figure 2. SPI Control Interface Timing

7.11 Timing Requirements: Audio Data Interface for Slave Mode

PARAMETER⁽¹⁾		MIN	MAX	UNIT
t_BCKP	BCK period	1 / (64 × f_S)		ns
t_BCKH	BCK pulse duration high	1.5 × t_SCKI		ns
t_BCKL	BCK pulse duration low	1.5 × t_SCKI		ns
t_LRSU	LRCK set up time to BCK rising edge	50		ns
t_LRHD	LRCK hold time to BCK rising edge	10		ns
t_LRCP	LRCK period	10		µs
t_CKDO	Delay time BCK falling edge to DOUT valid	–10	40	ns
t_LRDO	Delay time LRCK edge to DOUT valid	–10	40	ns
t_R	Rise time of all signals		20	ns
t_F	Fall time of all signals		20	ns

(1) Timing measurement reference level is 1.4 V for input and 0.5VDD for output. Rise and fall times are measured from 10% to 90% of the IN/OUT signals swing. Load capacitance of DOUT is 20 pF. t_SCKI means SCKI period.

PCM1860-Q1 PCM1861-Q1 PCM1862-Q1 PCM1863-Q1 PCM1864-Q1 PCM1865-Q1 slave_tim_las831.gif

Figure 3. Audio Data Interface Timing, Slave Mode: LRCK and BCK as Inputs

7.12 Timing Requirements: Audio Data Interface for Master Mode

PARAMETER⁽¹⁾		MIN	TYP	MAX	UNIT
t_BCKP	BCK period	150	1 / (64 × f_S)	2000	ns
t_BCKH	BCK pulse duration high	65		1000	ns
t_BCKL	BCK pulse duration low	65		1000	ns
t_CKLR	Delay time BCK falling edge to LRCK valid	–10		20	ns
t_LRCP	LRCK period	10	1/f_S	125	µs
t_CKDO	Delay time BCK falling edge to DOUT valid	–10		20	ns
t_LRDO	Delay time LRCK edge to DOUT valid	–10		20	ns
t_R	Rise time of all signals			20	ns
t_F	Fall time of all signals			20	ns
t_SCKBCK	Delay time SCKI rising edge to BCK edge⁽²⁾	5		30	ns

(1) Timing measurement reference level is 0.5 V_DD. Rise and fall times are measured from 10% to 90% of the IN/OUT signals swing. Load capacitance of all signals are 20 pF.

(2) Timing measurement reference level is 1.4 V for input and 0.5 V_DD for output. Load capacitance of BCK is 20 pF. This timing is applied when SCKI frequency is less than 25 MHz.

PCM1860-Q1 PCM1861-Q1 PCM1862-Q1 PCM1863-Q1 PCM1864-Q1 PCM1865-Q1 master_tim_las831.gif

Figure 4. Audio Data Interface Timing, Master Mode: LRCK and BCK as Outputs

PCM1860-Q1 PCM1861-Q1 PCM1862-Q1 PCM1863-Q1 PCM1864-Q1 PCM1865-Q1 audio_clk_if_las831.gif

Figure 5. Audio Data Interface Timing, Master Mode: BCK as Outputs

7.13 Typical Characteristics

all specifications at T_A = 25°C, AVDD = 3.3 V, DVDD = 3.3 V, IOVDD = 3.3 V, master mode, single-speed mode, f_S = 48 kHz, system clock = 256 × f_S, and 24-bit data (unless otherwise noted)