7.3.1.1 Audio Serial Interface

The audio interface port is a three-wire serial port. It includes LRCK (pin 4), BCK (pin 6), and DATA (pin 5). BCK is the serial audio bit clock, and it is used to clock the serial data present on DATA into the serial shift register of the audio interface. Serial data are clocked into the PCM1795 on the rising edge of BCK. LRCK is the serial audio left/right word clock.

The PCM1795 device requires the synchronization of LRCK and the system clock, but does not need a specific phase relation between LRCK and the system clock.

If the relationship between LRCK and the system clock changes more than ±6 BCK, internal operation is initialized within 1/f_S and analog outputs are forced to the bipolar zero level until resynchronization between LRCK and the system clock is completed.

7.3.1.2 PCM Audio Data Formats and Timing

The PCM1795 device supports industry-standard audio data formats, including standard right-justified, I²S, and left-justified. The data formats are illustrated in Figure 35 to Figure 37. Data formats are selected using the format bits, FMT[2:0], in control register 18. The default data format is 32-bit I²S. All formats require binary twos complement, MSB-first audio data. Figure 34 and Table 1 show a detailed timing diagram for the serial audio interface.

Figure 34. Audio Interface Timing

Figure 35. Audio Data Input Format: Standard Data Format (Right-Justified), Left Channel = High, Right Channel = Low

Figure 36. Audio Data Input Format: Left-Justified Data Format, Left Channel = High, Right Channel = Low

Figure 37. Audio Data Input Format: I²S Data Format, Left Channel = Low, Right Channel = High

7.3.1.3 External Digital Filter Interface and Timing

The PCM1795 device supports an external digital filter interface that consists of a three- or four-wire synchronous serial port that allows the use of an external digital filter. External filters include the Texas Instruments’ DF1704 and DF1706, the Pacific Microsonics PMD200, or a programmable digital signal processor.

In the external DF mode, LRCK (pin 4), BCK (pin 6) and DATA (pin 5) are defined as: WDCK, the word clock; BCK, the bit clock; and DATA, the monaural data. The external digital filter interface is selected by using the DFTH bit of control register 20, which functions to bypass the internal digital filter of the PCM1795 device .

When the DFMS bit of control register 19 is set, the PCM1795 device can process stereo data. In this case, ZEROL (pin 1) and ZEROR (pin 2) are defined as left-channel data and right-channel data input, respectively.

Detailed information for the external digital filter interface mode is provided in Application For External Digital Filter Interface.

7.3.1.4 Direct Stream Digital (DSD) Format Interface and Timing

The PCM1795 device supports the DSD format interface operation, which includes out-of-band noise filtering using an internal analog FIR filter. For DSD operation, SCK (pin 7) is redefined as BCK, DATA (pin 5) as DATAL (left channel audio data), and LRCK (pin 4) as DATAR (right channel audio data). BCK (pin 6) must be forced low in the DSD mode. The DSD format interface is activated by setting the DSD bit of control register 20.

Detailed information for the DSD mode is provided in Application For DSD Format (DSD Mode) Interface.

7.3.1.5 TDMCA Interface

The PCM1795 device supports the time-division-multiplexed command and audio (TDMCA) data format to enable control of and communication with a number of external devices over a single serial interface.

Detailed information for the TDMCA format is provided in TDMCA Interface Format.

7.3.1.6 Analog Output

Table 2 and Figure 38 show the relationship between the digital input code and analog output.

Figure 38. Relationship Between Digital Input and Analog Output

7.5.1.1 System Clock Input

The PCM1795 requires a system clock to operate the digital interpolation filters and advanced segment DAC modulators. The system clock is applied at the SCK input (pin 7). The PCM1795 has a system clock detection circuit that automatically senses the frequency at which the system clock is operating. Table 3 shows examples of system clock frequencies for common audio sampling rates. If the oversampling rate of the delta-sigma (ΔΣ) modulator is selected as 128 f_S, the system clock frequency is required to be greater than 256 f_S.

Figure 39 and Table 4 show the timing requirements for the system clock input. For optimal performance, it is important to use a clock source with low phase jitter and noise. The Texas Instruments PLL1700 family of multiclock generators is an excellent choice to provide the PCM1795 system clock.

Figure 39. System Clock Input Timing

7.5.1.2 Power-On and External Reset Functions

The PCM1795 includes a power-on reset function, as shown in Figure 40. With V_DD > 2 V, the power-on reset function is enabled. The initialization sequence requires 1024 system clocks from the time V_DD > 2 V. After the initialization period, the PCM1795 is set to its default reset state, as described in Mode Control Registers.

The PCM1795 also includes an external reset capability using the RST input (pin 14). This feature allows an external controller or master reset circuit to force the PCM1795 to initialize to the default reset state.

Figure 41 and Table 5 show the external reset operation and timing. The RST pin is set to logic 0 for a minimum of 20 ns. The RST pin is then set to a logic 1 state, thus starting the initialization sequence that requires 1024 system clock periods. The external reset is especially useful in applications where there is a delay between the PCM1795 power-up and system clock activation.

Figure 40. Power-On Reset Timing

Figure 41. External Reset Timing

7.5.2.1 Zero Detect

The PCM1795 has a zero-detect function. When the PCM1795 detects the zero conditions as shown in Table 6, the PCM1795 sets ZEROL (pin 1) and ZEROR (pin 2) high.

7.5.3.1 SPI Interface

The SPI interface is a four-wire synchronous serial port that operates asynchronously to the serial audio interface and the system clock (SCK). The serial control interface is used to program and read the on-chip mode registers. The control interface includes MDO (pin 13), MDI (pin 11), MC (pin 12), and MS (pin 10). MDO is the serial data output, used to read back the values of the mode registers; MDI is the serial data input, used to program the mode registers; MC is the serial bit clock, used to shift data in and out of the control port; and MS is the mode control enable, used to enable the internal mode register access.

7.5.3.2 Register Read/Write Operation

All read/write operations for the serial control port use 16-bit data words. Figure 42 shows the control data word format. The most significant bit (MSB) is the read/write (R/W) bit. For write operations, the R/W bit must be set to '0'. For read operations, the R/W bit must be set to '1'. There are 7 bits, labeled IDX[6:0], that hold the register index (or address) for the read and write operations. The least significant 8 bits, D[7:0], contain the data to be written to, or the data that was read from, and the register specified by IDX[6:0].

Figure 43 shows the functional timing diagram for writing or reading the serial control port. MS is held at a logic 1 state until a register must be written to or read from. To start the register write or read cycle, MS is set to logic 0. Sixteen clocks are then provided on MC, corresponding to the 16 bits of the control data word on MDI and readback data on MDO. After the eighth clock cycle has completed, the data from the indexed-mode control register appears on MDO during the read operation. After the 16th clock cycle has completed, the data are latched into the indexed-mode control register during the write operation. To write or read subsequent data, MS must be set to '1' once.

Figure 42. Control Data Word Format for MDI

NOTE: Bit 15 is used for selection of write or read. Setting R/W = 0 indicates a write, while R/W = 1 indicates a read. Bits 14–8 are used for the register address. Bits 7–0 are used for register data.

Figure 43. Serial Control Format

Figure 44. Control Interface Timing

Table 8. Control Terminals

7.5.4.1 Slave Address

The PCM1795 has 7 bits for its own slave address, as shown in Figure 45. The first 5 bits (MSBs) of the slave address are factory preset to 10011. The next 2 bits of the address byte are the device select bits that can be user-defined by the ADR1 and ADR0 terminals. A maximum of four PCM1795 devicess can be connected on the same bus at one time. Each PCM1795 responds when it receives its own slave address.

Figure 45. Slave Address

7.5.4.2 Packet Protocol

A master device must control packet protocol that consists of a start condition, slave address, read/write bit, data if write or acknowledge if read, and stop condition. The PCM1795 supports only slave receivers and slave transmitters.

Figure 46. Basic I²C Framework

7.5.4.3 Write Register

A master can write to any PCM1795 registers using single or multiple accesses. The master sends a PCM1795 slave address with a write bit, a register address, and the data. If multiple access is required, the address is that of the starting register, followed by the data to be transferred. When the data are received properly, the index register is incremented by '1' automatically. When the index register reaches 0x7F, the next value is 0x00. When undefined registers are accessed, the PCM1795 does not send an acknowledgment. Figure 47 shows a diagram of the write operation.

Figure 47. Write Operation

7.5.4.4 Read Register

A master can read the PCM1795 register. The value of the register address is stored in an indirect index register in advance. The master sends a PCM1795 slave address with a read bit after storing the register address. Then the PCM1795 transfers the data that the index register points to. When the data are transferred during a multiple access, the index register is incremented by '1' automatically. (When first going into read mode immediately following a write, the index register is not incremented. The master can read the register that was previously written.) When the index register reaches 0x7F, the next value is 0x00. The PCM1795 outputs some data when the index register is 0x10 to 0x1F, even if it is not defined in Table 10. Figure 48 shows a diagram of the read operation.

Figure 48. Read Operation

7.5.4.5 Noise Suppression

The PCM1795 incorporates noise suppression using the system clock (SCK). However, there must be no more than two noise spikes in 600 ns. The noise suppression works for SCK frequencies between 8 MHz and 40 MHz in fast mode. However, it works incorrectly under the following conditions:

Case 1:

1. t_(SCK) > 120 ns (t_(SCK): period of SCK)
2. t_(HI) + t_(D–HD) < t_(SCK) × 5
3. Spike noise exists on the first half of the SCL high pulse.
4. Spike noise exists on the SDA high pulse just before SDA goes low.

Figure 49. Case 1

When these conditions occur at the same time, the data are recognized as low.

Case 2:

1. t_(SCK) > 120 ns
2. t_(S–HD) or t_(RS–HD) < t_(SCK) × 5
3. Spike noise exists on both SCL and SDA during the hold time.

Figure 50. Case 2

When these conditions occur at the same time, the PCM1795 fails to detect a start condition.

Case 3:

1. t_(SCK) < 50 ns
2. t_(SP) > t_(SCK)
3. Spike noise exists on SCL just after SCL goes low.
4. Spike noise exists on SDA just before SCL goes low.

Figure 51. Case 3

When these conditions occur at the same time, the PCM1795 erroneously detects a start or stop condition.

7.6.1.1 User-Programmable Mode Controls

The PCM1795 device includes a number of user-programmable functions that are accessed via mode control registers. The registers are programmed using the serial control interface, as previously discussed in SPI Interface and I2C Interface. Table 9 lists the available mode-control functions, along with the default reset conditions and associated register index.

7.6.1.2 Register Map

The mode control register map is shown in Table 10. Registers 16 to 21 include an R/W bit that determines whether a register read (R/W = 1) or write (R/W = 0) operation is performed. Registers 22 and 23 are read-only.

7.6.1.3 Register Definitions