ZHCSOM7H July 2001 – September 2024 PCF8574A
PRODUCTION DATA
請參考 PDF 數據表獲取器件具體的封裝圖。
I2C communication with this device is initiated by a commander sending a start condition, a high-to-low transition on the SDA I/O while the SCL input is high. After the start condition, the device address byte is sent, most-significant bit (MSB) first, including the data direction bit (R/ W). This device does not respond to the general call address. After receiving the valid address byte, this device responds with an acknowledge, a low on the SDA I/O during the high of the acknowledge-related clock pulse. The address inputs (A0–A2) of the responder device must not be changed between the start and the stop conditions.
The data byte follows the address acknowledge. If the R/ W bit is high, the data from this device are the values read from the P port. If the R/ W bit is low, the data are from the commander, to be output to the P port. The data byte is followed by an acknowledge sent from this device. If other data bytes are sent from the commander, following the acknowledge, they are ignored by this device. Data are output only if complete bytes are received and acknowledged. The output data will be valid at time, tpv, after the low-to-high transition of SCL and during the clock cycle for the acknowledge.
A stop condition, a low-to-high transition on the SDA I/O while the SCL input is high, is sent by the commander.