ZHCSXH5K December 2005 – December 2024 PCA9557
PRODUCTION DATA
- 1
- 1 特性
- 2 應(yīng)用
- 3 說(shuō)明
- 4 Pin Configuration and Functions
- 5 Specifications
- 6 Parameter Measurement Information
- 7 Detailed Description
- 8 Application and Implementation
- 9 Device and Documentation Support
- 10Revision History
- 11Mechanical, Packaging, and Orderable Information
封裝選項(xiàng)
機(jī)械數(shù)據(jù) (封裝 | 引腳)
散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)
訂購(gòu)信息
7.4.1 Device Address
The address of the PCA9557 is shown in Figure 7-7.
Figure 7-7 PCA9557 AddressThe address reference of the PCA9557 is shown in Table 7-2.
Table 7-2 Address Reference
| INPUTS | I2C BUS TARGET ADDRESS | ||
|---|---|---|---|
| A2 | A1 | A0 | |
| L | L | L | 24 (decimal), 18 (hexadecimal) |
| L | L | H | 25 (decimal), 19 (hexadecimal) |
| L | H | L | 26 (decimal), 1A (hexadecimal) |
| L | H | H | 27 (decimal), 1B (hexadecimal) |
| H | L | L | 28 (decimal), 1C (hexadecimal) |
| H | L | H | 29 (decimal), 1D (hexadecimal) |
| H | H | L | 30 (decimal), 1E (hexadecimal) |
| H | H | H | 31 (decimal), 1F (hexadecimal) |
The last bit of the target address defines the operation (read or write) to be performed. A high (1) selects a read operation, while a low (0) selects a write operation.