ZHCSHU7J August 2005 – March 2021 PCA9555
PRODUCTION DATA
- 1 特性
- 2 應用
- 3 說明
- 4 Revision History
- 5 Pin Configuration and Functions
- 6 Specifications
- 7 Parameter Measurement Information
- 8 Detailed Description
- 9 Application Information Disclaimer
- 10Power Supply Recommendations
- 11Layout
- 12Device and Documentation Support
- 13Mechanical, Packaging, and Orderable Information
封裝選項
機械數(shù)據 (封裝 | 引腳)
散熱焊盤機械數(shù)據 (封裝 | 引腳)
- RGE|24
訂購信息
10.1 Power-On Reset Requirements
In the event of a glitch or data corruption, PCA9555 can be reset to its default conditions by using the power-on reset feature. Power-on reset requires that the device go through a power cycle to be completely reset. This reset also happens when the device is powered on for the first time in an application.
The two types of power-on reset are shown in Figure 10-1 and Figure 10-2.
Figure 10-1 VCC Is Lowered Below 0.2 V Or 0 V And Then Ramped Up To VCC
Figure 10-2 VCC Is Lowered Below The Por Threshold, Then Ramped Back Up To VCCTable 10-1 specifies the performance of the power-on reset feature for PCA9555 for both types of power-on reset.
| PARAMETER | MIN | TYP | MAX | UNIT | ||
|---|---|---|---|---|---|---|
| VCC_FT | Fall rate | See Figure 10-1 | 1 | 100 | ms | |
| VCC_RT | Rise rate | See Figure 10-1 | 0.01 | 100 | ms | |
| VCC_TRR_GND | Time to re-ramp (when VCC drops to GND) | See Figure 10-1 | 0.001 | ms | ||
| VCC_TRR_POR50 | Time to re-ramp (when VCC drops to VPOR_MIN – 50 mV) | See Figure 10-2 | 0.001 | ms | ||
| VCC_GH | Level that VCCP can glitch down to, but not cause a functional disruption when VCCX_GW = 1 μs | See Figure 10-3 | 1.2 | V | ||
| VCC_GW | Glitch width that will not cause a functional disruption when VCCX_GH = 0.5 × VCCx | See Figure 10-3 | μs | |||
| VPORF | Voltage trip point of POR on falling VCC | 0.767 | 1.144 | V | ||
| VPORR | Voltage trip point of POR on rising VCC | 1.033 | 1.428 | V | ||
Glitches in the power supply can also affect the power-on reset performance of this device. The glitch width (VCC_GW) and height (VCC_GH) are dependent on each other. The bypass capacitance, source impedance, and the device impedance are factors that affect power-on reset performance. Figure 10-3 and Table 10-1 provide more information on how to measure these specifications.
Figure 10-3 Glitch Width And Glitch HeightVPOR is critical to the power-on reset. VPOR is the voltage level at which the reset condition is released and all the registers and the I2C/SMBus state machine are initialized to their default states. The value of VPOR differs based on the VCC being lowered to or from 0. Figure 10-4 and Table 10-1 provide more details on this specification.
Figure 10-4 VPOR