ZHCSIR8F August   2009  – September 2018 MSP430F5418 , MSP430F5419 , MSP430F5435 , MSP430F5436 , MSP430F5437 , MSP430F5438

PRODUCTION DATA.  

1. 1器件概述
   1. 1.1 特性
   2. 1.2 應用范圍
   3. 1.3 說明
   4. 1.4 功能框圖
2. 2修訂歷史記錄
3. 3Device Comparison
   1. 3.1 Related Products
4. 4Terminal Configuration and Functions
   1. 4.1 Pin Diagrams
   2. 4.2 Signal Descriptions
      1. Table 4-1 Signal Descriptions
5. 5Specifications
   1. 5.1  Absolute Maximum Ratings
   2. 5.2  ESD Ratings
   3. 5.3  Recommended Operating Conditions
   4. 5.4  Active Mode Supply Current Into VCC Excluding External Current
   5. 5.5  Low-Power Mode Supply Currents (Into VCC) Excluding External Current
   6. 5.6  Thermal Resistance Characteristics
   7. 5.7  Schmitt-Trigger Inputs – General-Purpose I/O
   8. 5.8  Inputs – Ports P1 and P2
   9. 5.9  Leakage Current – General-Purpose I/O
   10. 5.10 Outputs – General-Purpose I/O (Full Drive Strength)
   11. 5.11 Outputs – General-Purpose I/O (Reduced Drive Strength)
   12. 5.12 Output Frequency – General-Purpose I/O
   13. 5.13 Typical Characteristics – Outputs, Reduced Drive Strength (PxDS.y = 0)
   14. 5.14 Typical Characteristics – Outputs, Full Drive Strength (PxDS.y = 1)
   15. 5.15 Crystal Oscillator, XT1, Low-Frequency Mode
   16. 5.16 Crystal Oscillator, XT1, High-Frequency Mode
   17. 5.17 Crystal Oscillator, XT2
   18. 5.18 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
   19. 5.19 Internal Reference, Low-Frequency Oscillator (REFO)
   20. 5.20 DCO Frequency
   21. 5.21 PMM, Brownout Reset (BOR)
   22. 5.22 PMM, Core Voltage
   23. 5.23 PMM, SVS High Side
   24. 5.24 PMM, SVM High Side
   25. 5.25 PMM, SVS Low Side
   26. 5.26 PMM, SVM Low Side
   27. 5.27 Wake-up Times From Low-Power Modes
   28. 5.28 Timer_A
   29. 5.29 Timer_B
   30. 5.30 USCI (UART Mode) Clock Frequency
   31. 5.31 USCI (UART Mode)
   32. 5.32 USCI (SPI Master Mode) Clock Frequency
   33. 5.33 USCI (SPI Master Mode)
   34. 5.34 USCI (SPI Slave Mode)
   35. 5.35 USCI (I2C Mode)
   36. 5.36 12-Bit ADC, Power Supply and Input Range Conditions
   37. 5.37 12-Bit ADC, External Reference
   38. 5.38 12-Bit ADC, Built-In Reference
   39. 5.39 12-Bit ADC, Timing Parameters
   40. 5.40 12-Bit ADC, Linearity Parameters
   41. 5.41 12-Bit ADC, Temperature Sensor and Built-In VMID
   42. 5.42 Flash Memory
   43. 5.43 JTAG and Spy-Bi-Wire Interface
6. 6Detailed Description
   1. 6.1  CPU
   2. 6.2  Operating Modes
   3. 6.3  Interrupt Vector Addresses
   4. 6.4  Memory Organization
   5. 6.5  Bootloader (BSL)
   6. 6.6  JTAG Operation
      1. 6.6.1 JTAG Standard Interface
      2. 6.6.2 Spy-Bi-Wire Interface
   7. 6.7  Flash Memory (Link to User's Guide)
   8. 6.8  RAM (Link to User's Guide)
   9. 6.9  Peripherals
      1. 6.9.1  Digital I/O (Link to User's Guide)
      2. 6.9.2  Oscillator and System Clock (Link to User's Guide)
      3. 6.9.3  Power-Management Module (PMM) (Link to User's Guide)
      4. 6.9.4  Hardware Multiplier (Link to User's Guide)
      5. 6.9.5  Real-Time Clock (RTC_A) (Link to User's Guide)
      6. 6.9.6  Watchdog Timer (WDT_A) (Link to User's Guide)
      7. 6.9.7  System Module (SYS) (Link to User's Guide)
      8. 6.9.8  DMA Controller (Link to User's Guide)
      9. 6.9.9  Universal Serial Communication Interface (USCI) (Links to User's Guide: UART Mode, SPI Mode, I2C Mode)
      10. 6.9.10 TA0 (Link to User's Guide)
      11. 6.9.11 TA1 (Link to User's Guide)
      12. 6.9.12 TB0 (Link to User's Guide)
      13. 6.9.13 ADC12_A (Link to User's Guide)
      14. 6.9.14 CRC16 (Link to User's Guide)
      15. 6.9.15 Embedded Emulation Module (EEM) (L Version) (Link to User's Guide)
      16. 6.9.16 Peripheral File Map
   10. 6.10 Input/Output Diagrams
       1. 6.10.1  Port P1, P1.0 to P1.7, Input/Output With Schmitt Trigger
       2. 6.10.2  Port P2, P2.0 to P2.7, Input/Output With Schmitt Trigger
       3. 6.10.3  Port P3, P3.0 to P3.7, Input/Output With Schmitt Trigger
       4. 6.10.4  Port P4, P4.0 to P4.7, Input/Output With Schmitt Trigger
       5. 6.10.5  Port P5, P5.0 and P5.1, Input/Output With Schmitt Trigger
       6. 6.10.6  Port P5, P5.2, Input/Output With Schmitt Trigger
       7. 6.10.7  Port P5, P5.3, Input/Output With Schmitt Trigger
       8. 6.10.8  Port P5, P5.4 to P5.7, Input/Output With Schmitt Trigger
       9. 6.10.9  Port P6, P6.0 to P6.7, Input/Output With Schmitt Trigger
       10. 6.10.10 Port P7, P7.0, Input/Output With Schmitt Trigger
       11. 6.10.11 Port P7, P7.1, Input/Output With Schmitt Trigger
       12. 6.10.12 Port P7, P7.2 and P7.3, Input/Output With Schmitt Trigger
       13. 6.10.13 Port P7, P7.4 to P7.7, Input/Output With Schmitt Trigger
       14. 6.10.14 Port P8, P8.0 to P8.7, Input/Output With Schmitt Trigger
       15. 6.10.15 Port P9, P9.0 to P9.7, Input/Output With Schmitt Trigger
       16. 6.10.16 Port P10, P10.0 to P10.7, Input/Output With Schmitt Trigger
       17. 6.10.17 Port P11, P11.0 to P11.2, Input/Output With Schmitt Trigger
       18. 6.10.18 Port J, J.0 JTAG Pin TDO, Input/Output With Schmitt Trigger or Output
       19. 6.10.19 Port J, J.1 to J.3 JTAG Pins TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger or Output
   11. 6.11 TLV (Device Descriptor) Structures
7. 7器件和文檔支持
   1. 7.1  入門和后續(xù)步驟
   2. 7.2  Device Nomenclature
   3. 7.3  工具和軟件
   4. 7.4  文檔支持
   5. 7.5  相關(guān)鏈接
   6. 7.6  社區(qū)資源
   7. 7.7  商標
   8. 7.8  靜電放電警告
   9. 7.9  Export Control Notice
   10. 7.10 Glossary
8. 8機械，封裝和可訂購信息