ZHCSLV4 December   2020 LP875761-Q1

PRODUCTION DATA  

1. 1 特性
2. 2 應(yīng)用
3. 3 說明
4. 4 Revision History
5. 5 Pin Configuration and Functions
6. 6 Specifications
   1. 6.1 Absolute Maximum Ratings
   2. 6.2 ESD Ratings
   3. 6.3 Recommended Operating Conditions
   4. 6.4 Thermal Information
   5. 6.5 Electrical Characteristics
   6. 6.6 I2C Serial Bus Timing Requirements
   7. 6.7 Typical Characteristics
7. 7 Detailed Description
   1. 7.1 Overview
   2. 7.2 Functional Block Diagram
   3. 7.3 Feature Descriptions
      1. 7.3.1 Multi-Phase DC/DC Converters
         1. 7.3.1.1 Overview
         2. 7.3.1.2 Multiphase Switcher Configurations
         3. 7.3.1.3 Buck Converter Load-Current Measurement
         4. 7.3.1.4 Spread-Spectrum Mode
      2. 7.3.2 Sync Clock Functionality
      3. 7.3.3 Power-Up
      4. 7.3.4 Regulator Control
         1. 7.3.4.1 Enabling and Disabling Regulators
      5. 7.3.5 Enable and Disable Sequences
      6. 7.3.6 Device Reset Scenarios
      7. 7.3.7 Diagnosis and Protection Features
         1. 7.3.7.1 Power-Good Information (PGOOD pin)
         2. 7.3.7.2 Warnings for Diagnosis (Interrupt)
            1. 7.3.7.2.1 Output Power Limit
            2. 7.3.7.2.2 Thermal Warning
         3. 7.3.7.3 Protection (Regulator Disable)
            1. 7.3.7.3.1 Short-Circuit and Overload Protection
            2. 7.3.7.3.2 Overvoltage Protection
            3. 7.3.7.3.3 Thermal Shutdown
         4. 7.3.7.4 Fault (Power Down)
            1. 7.3.7.4.1 Undervoltage Lockout
      8. 7.3.8 GPIO Signal Operation
      9. 7.3.9 Digital Signal Filtering
   4. 7.4 Device Functional Modes
      1. 7.4.1 Modes of Operation
   5. 7.5 Programming
      1. 7.5.1 I2C-Compatible Interface
         1. 7.5.1.1 Data Validity
         2. 7.5.1.2 Start and Stop Conditions
         3. 7.5.1.3 Transferring Data
         4. 7.5.1.4 I2C-Compatible Chip Address
         5. 7.5.1.5 Auto-Increment Feature
   6. 7.6 Register Maps
      1. 7.6.1 Register Descriptions
         1.       53
         2. 7.6.1.1  DEV_REV
         3. 7.6.1.2  OTP_REV
         4. 7.6.1.3  BUCK0_CTRL1
         5. 7.6.1.4  BUCK0_CTRL2
         6. 7.6.1.5  BUCK1_CTRL2
         7. 7.6.1.6  BUCK2_CTRL2
         8. 7.6.1.7  BUCK3_CTRL2
         9. 7.6.1.8  BUCK0_DELAY
         10. 7.6.1.9  GPIO2_DELAY
         11. 7.6.1.10 GPIO3_DELAY
         12. 7.6.1.11 RESET
         13. 7.6.1.12 CONFIG
         14. 7.6.1.13 INT_TOP1
         15. 7.6.1.14 INT_TOP2
         16. 7.6.1.15 INT_BUCK_0_1
         17. 7.6.1.16 INT_BUCK_2_3
         18. 7.6.1.17 TOP_STAT
         19. 7.6.1.18 BUCK_0_1_STAT
         20. 7.6.1.19 BUCK_2_3_STAT
         21. 7.6.1.20 TOP_MASK1
         22. 7.6.1.21 TOP_MASK2
         23. 7.6.1.22 BUCK_0_1_MASK
         24. 7.6.1.23 BUCK_2_3_MASK
         25. 7.6.1.24 SEL_I_LOAD
         26. 7.6.1.25 I_LOAD_2
         27. 7.6.1.26 I_LOAD_1
         28. 7.6.1.27 PGOOD_CTRL1
         29. 7.6.1.28 PGOOD_CTRL2
         30. 7.6.1.29 PGOOD_FLT
         31. 7.6.1.30 PLL_CTRL
         32. 7.6.1.31 PIN_FUNCTION
         33. 7.6.1.32 GPIO_CONFIG
         34. 7.6.1.33 GPIO_IN
         35. 7.6.1.34 GPIO_OUT
8. 8 Application and Implementation
   1. 8.1 Application Information
   2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
         1. 8.2.1.1 Inductor Selection
         2. 8.2.1.2 Input Capacitor Selection
         3. 8.2.1.3 Output Capacitor Selection
         4. 8.2.1.4 Snubber Components
         5. 8.2.1.5 Supply Filtering Components
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
9. 9 Power Supply Recommendations
10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
11. 11Device and Documentation Support
    1. 11.1 接收文檔更新通知
    2. 11.2 支持資源
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 術(shù)語表
12. 12Mechanical, Packaging, and Orderable Information