ZHCSHY8 March 2018 LP87561-Q1 , LP87562-Q1 , LP87563-Q1 , LP87564-Q1 , LP87565-Q1
PRODUCTION DATA.
Address: 0x23
| D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
| Reserved | BUCK1_PG
_MASK |
Reserved | BUCK1_ILIM
_MASK |
Reserved | BUCK0_PG
_MASK |
Reserved | BUCK0_ILIM
_MASK |
| Bits | Field | Type | Default | Description |
|---|---|---|---|---|
| 7 | Reserved | R/W | 0h | |
| 6 | BUCK1_PG_MASK | R/W | X | Masking for the BUCK1 power-good interrupt (the BUCK1_PG_INT bit in the INT_BUCK_0_1 register)
This bit does not affect BUCK1_PG_STAT status bit in BUCK_0_1_STAT register. 0h = Interrupt generated 1h = Interrupt not generated |
| 5 | Reserved | R | 0h | |
| 4 | BUCK1_ILIM_MASK | R/W | X | Masking for the BUCK1 current-limit-detection interrupt (the BUCK1_ILIM_INT bit in the INT_BUCK_0_1 register)
This bit does not affect the BUCK1_ILIM_STAT status bit in the BUCK_0_1_STAT register. 0h = Interrupt generated 1h = Interrupt not generated |
| 3 | Reserved | R/W | 0h | |
| 2 | BUCK0_PG_MASK | R/W | X | Masking for the BUCK0 power-good interrupt (the BUCK0_PG_INT bit in the INT_BUCK_0_1 register)
This bit does not affect the BUCK0_PG_STAT status bit in the BUCK_0_1_STAT register. 0h = Interrupt generated 1h = Interrupt not generated |
| 1 | Reserved | R | 0h | |
| 0 | BUCK0_ILIM_MASK | R/W | X | Masking for the BUCK0 current-limit-detection interrupt (the BUCK0_ILIM_INT bit in the INT_BUCK_0_1 register)
This bit does not affect the BUCK0_ILIM_STAT status bit in the BUCK_0_1_STAT register. 0h = Interrupt generated 1h = Interrupt not generated |