ZHCSE96F September 2015 – April 2021 LP5910
PRODUCTION DATA
The dynamic performance of the LP5910 is dependant on the layout of the PCB. PCB layout practices that are adequate for typical LDOs may degrade the PSRR, noise, or transient performance of the LP5910.
Best performance is achieved by placing CIN and COUT on the same side of the PCB as the LP5910 device, and as close as is practical to the package. The ground connections for CIN and COUT must be back to the LP5910 GND pin using as wide and as short of a copper trace as is practical.
Avoid connections using long trace lengths, narrow trace widths, and/or connections through vias. These add parasitic inductances and resistance that results in inferior performance especially during transient conditions.