ZHCSIQ2B September 2018 – January 2019 LP5030 , LP5036
PRODUCTION DATA.
- 1 特性
- 2 應用
- 3 說明
- 4 修訂歷史記錄
- 5 說明 （續）
- 6 Pin Configuration and Functions
- 7 Specifications
-
8 Detailed Description
- 8.1 Overview
- 8.2 Functional Block Diagram
- 8.3
Feature Description
- 8.3.1 Each Channel PWM Control
- 8.3.2 LED Bank Control
- 8.3.3 Current Range Setting
- 8.3.4 Automatic Power-Save Mode
- 8.3.5 Protection Features
- 8.4 Device Functional Modes
- 8.5 Programming
- 8.6
Register Maps
- 8.6.1 DEVICE_CONFIG0 (Address = 0h) [reset = 0h]
- 8.6.2 DEVICE_CONFIG1 (Address = 1h) [reset = 3Ch]
- 8.6.3 LED_CONFIG0 (Address = 2h) [reset = 00h]
- 8.6.4 LED_CONFIG1 (Address = 3h) [reset = 00h]
- 8.6.5 BANK_BRIGHTNESS (Address = 4h) [reset = FFh]
- 8.6.6 BANK_A_COLOR (Address = 5h) [reset = 00h]
- 8.6.7 BANK_B_COLOR (Address = 6h) [reset = 00h]
- 8.6.8 BANK_C_COLOR (Address = 7h) [reset = 00h]
- 8.6.9 LED0_BRIGHTNESS (Address = 8h) [reset = FFh]
- 8.6.10 LED1_BRIGHTNESS (Address = 9h) [reset = FFh]
- 8.6.11 LED2_BRIGHTNESS (Address = 0Ah) [reset = FFh]
- 8.6.12 LED3_BRIGHTNESS (Address = 0Bh) [reset = FFh]
- 8.6.13 LED4_BRIGHTNESS (Address = 0Ch) [reset = FFh]
- 8.6.14 LED5_BRIGHTNESS (Address = 0Dh) [reset = FFh]
- 8.6.15 LED6_BRIGHTNESS (Address = 0Eh) [reset = FFh]
- 8.6.16 LED7_BRIGHTNESS (Address = 0Fh) [reset = FFh]
- 8.6.17 LED8_BRIGHTNESS (Address = 10h) [reset = FFh]
- 8.6.18 LED9_BRIGHTNESS (Address = 11h) [reset = FFh]
- 8.6.19 LED10_BRIGHTNESS (Address = 12h) [reset = FFh]
- 8.6.20 LED11_BRIGHTNESS (Address = 13h) [reset = FFh]
- 8.6.21 OUT0_COLOR (Address = 14h) [reset = 00h]
- 8.6.22 OUT1_COLOR (Address = 15h) [reset = 00h]
- 8.6.23 OUT2_COLOR (Address = 16h) [reset = 00h]
- 8.6.24 OUT3_COLOR (Address = 17h) [reset = 00h]
- 8.6.25 OUT4_COLOR (Address = 18h) [reset = 00h]
- 8.6.26 OUT5_COLOR (Address = 19h) [reset = 00h]
- 8.6.27 OUT6_COLOR (Address = 1Ah) [reset = 00h]
- 8.6.28 OUT7_COLOR (Address = 1Bh) [reset = 00h]
- 8.6.29 OUT8_COLOR (Address = 1Ch) [reset = 00h]
- 8.6.30 OUT9_COLOR (Address = 1Dh) [reset = 00h]
- 8.6.31 OUT10_COLOR (Address = 1Eh) [reset = 00h]
- 8.6.32 OUT11_COLOR (Address = 1Fh) [reset = 00h]
- 8.6.33 OUT12_COLOR (Address = 20h) [reset = 00h]
- 8.6.34 OUT13_COLOR (Address = 21h) [reset = 00h]
- 8.6.35 OUT14_COLOR (Address = 22h) [reset = 00h]
- 8.6.36 OUT15_COLOR (Address = 23h) [reset = 00h]
- 8.6.37 OUT16_COLOR (Address = 24h) [reset = 00h]
- 8.6.38 OUT17_COLOR (Address = 25h) [reset = 00h]
- 8.6.39 OUT18_COLOR (Address = 26h) [reset = 00h]
- 8.6.40 OUT19_COLOR (Address = 27h) [reset = 00h]
- 8.6.41 OUT20_COLOR (Address = 28h) [reset = 00h]
- 8.6.42 OUT21_COLOR (Address = 29h) [reset = 00h]
- 8.6.43 OUT22_COLOR (Address = 2Ah) [reset = 00h]
- 8.6.44 OUT23_COLOR (Address = 2Bh) [reset = 00h]
- 8.6.45 OUT24_COLOR (Address = 2Ch) [reset = 00h]
- 8.6.46 OUT25_COLOR (Address = 2Dh) [reset = 00h]
- 8.6.47 OUT26_COLOR (Address = 2Eh) [reset = 00h]
- 8.6.48 OUT27_COLOR (Address = 2Fh) [reset = 00h]
- 8.6.49 OUT28_COLOR (Address = 30h) [reset = 00h]
- 8.6.50 OUT29_COLOR (Address = 31h) [reset = 00h]
- 8.6.51 OUT30_COLOR (Address = 32h) [reset = 00h]
- 8.6.52 OUT31_COLOR (Address = 33h) [reset = 00h]
- 8.6.53 OUT32_COLOR (Address = 34h) [reset = 00h]
- 8.6.54 OUT33_COLOR (Address = 35h) [reset = 00h]
- 8.6.55 OUT34_COLOR (Address = 36h) [reset = 00h]
- 8.6.56 OUT35_COLOR (Address = 37h) [reset = 00h]
- 8.6.57 RESET (Address = 38h) [reset = 00h]
- 9 Application and Implementation
- 10Power Supply Recommendations
- 11Layout
- 12器件和文檔支持
- 13機械、封裝和可訂購信息
8.5.1.3 Transferring Data
Every byte put on the SDA line must be eight bits long, with the most-significant bit (MSB) being transferred first. Each byte of data must be followed by an acknowledge bit. The acknowledge-related clock pulse is generated by the master. The master releases the SDA line (HIGH) during the acknowledge clock pulse. The device pulls down the SDA line during the 9th clock pulse, signifying an acknowledge. The device generates an acknowledge after each byte has been received.
There is one exception to the acknowledge-after-every-byte rule. When the master is the receiver, it must indicate to the transmitter an end of data by not acknowledging (negative acknowledge) the last byte clocked out of the slave. This negative acknowledge still includes the acknowledge clock pulse (generated by the master), but the SDA line is not pulled down.
After the START condition, the bus master sends a chip address. This address is seven bits long followed by an eighth bit, which is a data direction bit (READ or WRITE). For the eighth bit, a 0 indicates a WRITE, and a 1 indicates a READ. The second byte selects the register to which the data is written. The third byte contains data to write to the selected register.
Figure 18. Acknowledge and Not Acknowledge on I2C Bus