ZHCSX69E November 2003 – October 2024 LP3943
PRODUCTION DATA
- 1
- 1特性
- 2應(yīng)用
- 3說明
- 4Pin Configuration and Functions
- 5Specifications
- 6Detailed Description
- Application and Implementation
- 7Device and Documentation Support
- 8Revision History
- Mechanical, Packaging, and Orderable Information
封裝選項(xiàng)
機(jī)械數(shù)據(jù) (封裝 | 引腳)
- RTW|24
散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)
- RTW|24
訂購信息
6.5.2 I2C START and STOP Conditions
START and STOP bits classify the beginning and the end of the I2C session. START condition is defined as SDA signal transitioning from HIGH to LOW while SCL line is HIGH. STOP condition is defined as the SDA transitioning from LOW to HIGH while SCL is HIGH. The I2C master always generates START and STOP bits. The I2C bus is considered to be busy after START condition and free after STOP condition. During data transmission, I2C master can generate repeated START conditions. First START and repeated START conditions are equivalent, function-wise.
Figure 6-2 I2C START and STOP Conditions