10.1 Layout Guidelines
To achieve optimal electrical and thermal performance, an optimized PCB layout is required. Figure 38 thru Figure 41, shows a typical PCB layout. Some considerations for an optimized layout are:
- Use large copper areas for power planes (VIN, VOUT, and PGND) to minimize conduction loss and thermal stress.
- Connect PGND pins 14 and 15 directly to pin 18 using thick copper traces.
- Connect the SW pins together using a small copper island under the device for thermal relief.
- Place ceramic input and output capacitors close to the device pins to minimize high frequency noise.
- Locate additional output capacitors between the ceramic capacitor and the load.
- Keep AGND and PGND separate from one another.
- Place RFBT, RFBB, RRT, and CFF as close as possible to their respective pins.
- Use multiple vias to connect the power planes to internal layers.