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ZHCSHO5C December 2017 – March 2023 LMZM23601

PRODUCTION DATA

封裝選項

請參考 PDF 數據表獲取器件具體的封裝圖。

機械數據 (封裝 | 引腳)

SIL|10

散熱焊盤機械數據 (封裝 | 引腳)

訂購信息

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6.5 Electrical Characteristics

Limits apply over the recommended operating junction temperature range of -40°C to +125°C, unless otherwise stated. Minimum and maximum limits are ensured through test, design or statistical correlation. Typical values represent the most likely parametric norm at T_J= 25°C, and are provided for reference purposes only. Unless otherwise stated, the following conditions apply: V_IN = 24 V.

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
FEEDBACK
V_FB	Initial output voltage accuracy (3.3-V and 5-V fixed output)	V_IN = 4 V to 36 V, open loop	–1.5%		1.5%
V_FB	Reference voltage (ADJ option)	V_IN = 4 V to 36 V, open loop	0.985	1	1.015	V
I_FB	Input current from FB to GND (ADJ option)	FB = 1 V		20		nA
CURRENT
I_Q	Operating quiescent current; measured at VIN pin	V_IN = 12 V, V_FB = +10%, V_OUT = 5 V		7		μA
		V_IN = 12 V, V_FB = +10%, V_OUT = 5 V, T_J = 85°C			16	μA
		V_IN = 12 V, V_FB = +10%, V_OUT = 5 V, T_J = 125°C			18
		V_IN = 24 V, V_FB = +10%, V_OUT = 5 V		12
		V_IN = 24 V, V_FB = +10%, V_OUT = 5 V, T_J = 85°C			24
		V_IN = 24 V, V_FB = +10%, V_OUT = 5 V, T_J = 125°C			26
I_B	Bias current into the VOUT pin	V_IN = 24 V, V_FB = +10%, V_OUT = 5 V, Mode = 0 V		48	80	μA
I_SD	Shutdown quiescent current; measured at VIN pin	EN = 0 V, V_IN = 12 V, T_J = 25°C		1.8		μA
		EN = 0 V, V_IN = 12 V, T_J = 85°C			3
		EN = 0 V, V_IN = 24 V, T_J = 25°C		5
		EN = 0 V, V_IN = 24 V, T_J = 85°C			10
UNDERVOLTAGE LOCKOUT (UVLO)
V_{IN_UVLO}	Minimum input voltage to operate	Rising	3.1	3.5	3.85	V
V_{IN_UVLO_HYST}	UVLO hysteresis		0.2	0.25	0.3	V
POWER GOOD FLAG (PGOOD)
V_{PGOOD_OV}	PGOOD upper threshold voltage	Rising, % of Vout	103.5%	106.7%	109%
V_{PGOOD_UV}	PGOOD lower threshold voltage	Falling, % of Vout	92%	94.7%	97%
V_{PGOOD_GUARD}	Magnitude of PGOOD lower threshold difference from steady state output voltage.	Steady state output voltage PGOOD threshold read at the same T_J and V_IN	4%
V_{PGOOD_HYST}	PGOOD hysteresis as a percent of output voltage set point			1.4%
V_{PGOOD_VALID}	Minimum input voltage for proper PGOOD function	50-μA pullup to PGOOD pin, EN = 0 V, T_J = 25°C		1.0	1.5	V
t_{RESET_FILTER}	Glitch filter time constant for PGOOD function			190		μs
V_OL	Low-level PGOOD function output voltage	50-μA pullup to PGOOD pin, V_IN = 1.5 V, EN = 0 V			0.4	V
		0.5-mA pullup to PGOOD pin, V_IN = 12 V, EN = 0 V			0.4
		1-mA pullup to PGOOD pin, V_IN = 12 V, EN = 3.3 V			0.4
R_{PGOOD_RDSON}	RDSON of the PGOOD output pull down			50	110	Ω
SWITCHING FREQUENCY
f_SW	Switching frequency	V_IN = 24 V, 5-V and 3.3-V fixed output options	675	750	825	kHz
		V_IN = 24 V, ADJ output options	890	1000	1090
		V_IN = 36 V, 5-V and 3.3-V fixed output options		750
		V_IN = 36 V, ADJ output options		800
FREQUENCY SYNCHRONIZATION AND MODE
f_SYNC	Sync frequency range	5-V and 3.3-V fixed output options V_OUT + V_DROPOUT < V_IN < 36 V	500		825	kHz
f_SYNC	Sync frequency range	ADJ output options V_OUT + V_DROPOUT< V_IN < 28 V	700		1100	kHz
D_SYNC	Sync input duty cycle range	2.3 V < HIGH state input < 5.5 V	25%		75%
V_{MODE_HIGH}	MODE/SYNC input logic HIGH voltage to enter FPWM mode		1.5			V
V_{MODE_LOW}	MODE/SYNC input logic LOW voltage to enter AUTO PFM mode				0.4	V
I_MODE	MODE/SYNC leakage current	V_IN = 12 V, V_MODE/SYNC = 3.3 V		1		μA
I_MODE	MODE/SYNC leakage current	V_IN = 12 V, V_MODE/SYNC = 12V		5		μA
t_MODE	MODE transition time to FPWM	V_IN = 12 V, V_OUT = 5 V, I_OUT= 20 mA		300		μs
t_MODE	MODE transition time to AUTO PFM	V_IN = 12 V, V_OUT = 5 V, I_OUT = 20 mA		300		μs
CURRENT LIMIT PROTECTION
I_L-HS	high-side switch current limit	Duty cycle approaches 0%	1.45	1.81	2.2	A
I_L-LS	low-side switch current limit		1	1.2	1.43	A
I_L-ZC	Zero-cross current limit	MODE/SYNC = logic LOW		–0.01		A
I_L-NEG	Low-side reverse current limit (positive current ino the SW pin to GND)	MODE/SYNC = logic HIGH	0.5	0.8		A
POWER STAGE CHARACTERISTICS
HS R_DS-ON	High-side MOSFET on-resistance			220		mΩ
LS R_DS-ON	Low-side MOSFET on-resistance			200		mΩ
t_ON-MIN	Minimum high-side on-time	I_OUT = 500 mA		50	80	ns
t_OFF-MIN	Minimum high-side off-time	I_OUT = 500 mA, ADJ		62	100	ns
D_MAX	Maximum switch duty cycle	5-V and 3.3-V fixed output options		93%
		ADJ option		91%
		While in frequency foldback		97%
L	Integrated inductor - inductance			10		μH
L_DCR	Integrated inductor - DCR			390		mΩ
ENABLE
V_EN	Enable input threshold voltage	Rising	1.7		1.92	V
V_{EN_HYST}	Enable input threshold hysteresis		0.42		0.52	V
V_{EN_WAKE}	Enable input wake-up threshold		0.4			V
I_EN	Enable pin input current	V_IN = V_EN = 12 V		2.7		μA
VCC REGULATOR
V_CC	Internal V_CC voltage	V_IN = 12 V, V_OUT < 3.3 V		3.05		V
V_CC	Internal V_CC voltage	V_IN = 12 V, V_OUT ≥ 3.3V		3.15		V
V_{CC_UVLO}	Internal V_CC voltage input UVLO	V_IN rising	2.23	2.73	3.25	V
V_{CC_UVLO_HYST}	Internal V_CC voltage input UVLO hysteresis	Hysteresis below VCC_UVLO	150		240	mV
SOFT START
t_SS	Soft-start time	Time for V_REF to ramp from 0% to 90%	1.8	3.5	5.5	ms
t_{EN_LV}	Turnon delay with low V_IN	V_IN < 4.2 V		4		ms
t_EN	Turnon delay	V_IN = 12 V		0.7		ms
t_W	Short circuit wait time (hiccup time)			8.0		ms
THERMAL PROTECTION
T_SD	Thermal shutdown	Rising threshold		155		°C
T_{SD_HYST}	Thermal shutdown hysteresis			15		°C