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SNVS711J March 2011 – August 2015 LMZ23603

PRODUCTION DATA.

封裝選項(xiàng)

機(jī)械數(shù)據(jù) (封裝 | 引腳)

NDW|7
- MMSF024

散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)

訂購信息

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾⁽³⁾⁽⁴⁾

	MIN	MAX	UNIT
VIN to PGND	–0.3	40	V
EN, SYNC to AGND	–0.3	5.5	V
SS/TRK, FBto AGND	–0.3	2.5	V
AGND to PGND	–0.3	0.3	V
Junction Temperature		150	°C
Peak Reflow Case Temperature (30 sec)		245	°C
Storage temperature, T_stg	–65	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) The human body model is a 100pF capacitor discharged through a 1.5 kΩ resistor into each pin. Test method is per JESD-22-114.

(3) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and specifications.

(4) For soldering specifications: see product folder at www.ti.com and SNOA549

6.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾⁽²⁾	±2000	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

	MIN	MAX	UNIT
VIN	6	36	V
EN, SYNC	0	5	V
Operation Junction Temperature	−40	125	°C

6.4 Thermal Information

THERMAL METRIC⁽¹⁾			LMZ23603	UNIT
			NDW
			7 PINS
R_θJA	Junction-to-ambient thermal resistance⁽²⁾	4-layer Evaluation Printed-Circuit-Board, 60 vias, No air flow	12.0	°C/W
R_θJA	Junction-to-ambient thermal resistance⁽²⁾	2-layer JEDEC Printed-Circuit-Board, No air flow	21.5	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	No air flow	1.9	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

(2) R_θJA measured on a 3.5-in × 3.5-in 4-layer board, with 3-oz. copper on outer layers and 2-oz. copper on inner layers, sixty thermal vias, no air flow, and 1-W power dissipation. Refer to PCB layout diagrams.

6.5 Electrical Characteristics

Limits are for T_J = 25°C unless otherwise specified. Minimum and Maximum limits are specified through test, design or statistical correlation. Typical values represent the most likely parametric norm at T_J = 25°C, and are provided for reference purposes only. Unless otherwise stated the following conditions apply: V_IN = 12V, V_OUT = 3.3V

PARAMETER		TEST CONDITIONS		MIN⁽¹⁾	TYP⁽²⁾	MAX⁽¹⁾	UNIT
SYSTEM PARAMETERS
ENABLE CONTROL
V_EN	EN threshold trip point	V_EN rising			1.279		V
V_EN	EN threshold trip point	V_EN rising	over the junction temperature (T_J) range of –40°C to +125°C	1.1		1.458	V
V_EN-HYS	EN input hysteresis current	V_EN > 1.279 V			–21		µA
SOFT-START
I_SS	SS source current	V_SS = 0 V			50		µA
I_SS	SS source current	V_SS = 0 V	over the junction temperature (T_J) range of –40°C to +125°C	40		60	µA
t_SS	Internal soft-start interval				1.6		ms
CURRENT LIMIT
I_CL	Current limit threshold	DC average	over the junction temperature (T_J) range of –40°C to +125°C	3.4			A
INTERNAL SWITCHING OSCILLATOR
f_osc	Free-running oscillator frequency	Sync input connected to ground.		711	812	914	kHz
f_sync	Synchronization range			650		950	kHz
V_IL-sync	Synchronization logic zero amplitude	Relative to AGND	over the junction temperature (T_J) range of –40°C to +125°C			0.4	V
V_IH-sync	Synchronization logic one amplitude	Relative to AGND.	over the junction temperature (T_J) range of –40°C to +125°C	1.5			V
V_{sync DC}	Synchronization duty cycle range			15%	50%	85%
D_max	Maximum Duty Factor				83%
REGULATION AND OVERVOLTAGE COMPARATOR
V_FB	In-regulation feedback voltage	V_SS >+ 0.8 V T_J = –40°C to 125°C I_O = 3 A			0.796		V
V_FB	In-regulation feedback voltage	V_SS >+ 0.8 V T_J = –40°C to 125°C I_O = 3 A	over the junction temperature (T_J) range of –40°C to +125°C	0.776		0.816	V
V_FB-OV	Feedback overvoltage protection threshold				0.86		V
I_FB	Feedback input bias current				5		nA
I_Q	Non-switchinginput current	V_FB= 0.86 V			2.6		mA
I_SD	Shutdown quiescent current	V_EN= 0 V			70		μA
THERMAL CHARACTERISTICS
T_SD	Thermal shutdown	Rising			165		°C
T_SD-HYST	Thermal shutdown hysteresis	Falling			15		°C
PERFORMANCE PARAMETERS⁽³⁾
ΔV_O	Output voltage ripple	Cout = 220 µF with 7-mΩ ESR + 100-µF X7R + 2 x 0.047-µF BW at 20 MHz			9		mV_PP
ΔV_O/ΔV_IN	Line regulation	V_IN = 12 V to 36 V, I_O= 0.001 A			±0.02%
ΔV_O/I_OUT	Load regulation	V_IN = 12 V, I_O= 0.001 A to 3 A			1		mV/A
η	Full load efficiency	V_IN = 12 V V_O = 3.3 V, I_O = 3 A			85%		mV/A
η	Full load efficiency	V_IN = 24 V V_O = 3.3 V, I_O = 3 A			78%
η	Peak efficiency	V_IN = 24 V V_O = 3.3 V, I_O = 2 A			80%
η	Peak efficiency	V_IN = 12 V V_O = 3.3 V, I_O = 1 A			86%

(1) Min and Max limits are 100% production tested at 25°C. Limits over the operating temperature range are specified through correlation using Statistical Quality Control (SQC) methods. Limits are used to calculate TI’s Average Outgoing Quality Level (AOQL).

(2) Typical numbers are at 25°C and represent the most likely parametric norm.

(3) Refer to BOM in Table 1.

6.6 Typical Characteristics

Unless otherwise specified, the following conditions apply: V_IN = 12 V; C_IN = 2 x 10 μF + 1-μF X7R Ceramic; C_O = 220-μF Specialty Polymer + 10-µF Ceramic; T_A = 25°C for waveforms. Efficiency and dissipation plots marked with * have cycle skipping at light loads resulting is slightly higher output ripple – See Design Steps section.

Figure 1. Efficiency 6-V Output at 25°C Ambient

Figure 3. Efficiency 5-V Output at 25°C Ambient

Figure 5. Efficiency 3.3-V Output at 25°C Ambient

Figure 7. Efficiency 2.5-V Output at 25°C Ambient

Figure 9. Efficiency 1.8-V Output at 25°C Ambient

Figure 11. Efficiency 1.5-V Output at 25°C Ambient

Figure 13. Efficiency 1.2-V Output at 25°C Ambient

Figure 15. Efficiency 1-V Output at 25°C Ambient

Figure 17. Efficiency 0.8-V Output at 25°C Ambient

Figure 19. Efficiency 6-V Output at 85°C

Figure 21. Efficiency 5-V Output at 85°C Ambient

Figure 23. Efficiency 3.3-V Output at 85°C Ambient

Figure 25. Efficiency 2.5-V Output at 85°C Ambient

Figure 27. Efficiency 1.8-V Output at 85°C Ambient

Figure 29. Efficiency 1.5-V Output at 85°C Ambient

Figure 31. Efficiency 1.2-V Output at 85°C Ambient

Figure 33. Efficiency 1-V Output at 85°C Ambient

Figure 35. Efficiency 0.8-V Output at 85°C Ambient

V_IN = 12 V, V_OUT = 5 V

Figure 37. Thermal Derating

V_IN = 24 V, V_OUT = 5 V

Figure 39. Thermal Derating

V_OUT = 3.3 V Normalized

Figure 41. Normalized Line and Load Regulation

12 V_IN, 3.3 V_O at 3 A BW = 250 MHz

Figure 43. Output Ripple from Evaluation Board

Figure 45. Short Circuit Current

Figure 2. Dissipation 6-V Output at 25°C Ambient

Figure 4. Dissipation 5-V Output at 25°C Ambient

Figure 6. Dissipation 3.3-V Output at 25°C Ambient

Figure 8. Dissipation 2.5-V Output at 25°C Ambient

Figure 10. Dissipation 1.8-V Output at 25°C Ambient

Figure 12. Dissipation 1.5-V Output at 25°C Ambient

Figure 14. Dissipation 1.2-V Output at 25°C Ambient

Figure 16. Dissipation 1-V Output at 25°C Ambient

Figure 18. Dissipation 0.8-V Output at 25°C Ambient

Figure 20. Dissipation 6-V Output at 85°C Ambient

Figure 22. Dissipation 5-V Output at 85°C Ambient

Figure 24. Dissipation 3.3-V Output at 85°C Ambient

Figure 26. Dissipation 2.5-V Output at 85°C Ambient

Figure 28. Dissipation 1.8-V Output at 85°C Ambient

Figure 30. Dissipation 1.5-V Output at 85°C Ambient

Figure 32. Dissipation 1.2-V Output at 85°C Ambient

Figure 34. Dissipation 1-V Output at 85°C Ambient

Figure 36. Dissipation 0.8-V Output at 85°C Ambient

V_IN = 12 V, V_OUT = 3.3 V

Figure 38. Thermal Derating

V_IN = 24 V, V_OUT = 3.3 V

Figure 40. Thermal Derating


12 V_IN, 3.3 V_O at 3 A, BW = 20 MHz

Figure 42. Output Ripple from Evaluation Board

12 V_IN, 3.3 V_O, 0.5- to 3-A Step

Figure 44. Transient Response from Evaluation Board