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ZHCSKL5D November 2019 – March 2022 LMX2694-EP

PRODUCTION DATA

封裝選項

請參考 PDF 數(shù)據(jù)表獲取器件具體的封裝圖。

機械數(shù)據(jù) (封裝 | 引腳)

RTC|48

散熱焊盤機械數(shù)據(jù) (封裝 | 引腳)

訂購信息

6.5 Electrical Characteristics

3.2 V ≤ V_CC ≤ 3.45 V, –50°C ≤ T_C ≤ 125°C. Typical values are at V_CC = 3.3 V, 25°C (unless otherwise noted)

PARAMETER		TEST CONDITIONS		MIN	TYP	MAX	UNIT
POWER SUPPLY
I_CC	Supply current	OUTA_PD = 0; OUTB_PD = 1; OUTA_MUX = OUTB_MUX = 1; OUTA_PWR = 31; CPG = 7; f_OSC = f_PD = 100 MHz; f_VCO = f_OUT = 14.5 GHz			360		mA
	Power on reset current	RESET = 1			289
	Power down current	POWERDOWN = 1			6
OUTPUT CHARACTERISTICS
p_OUT	Single-ended output power⁽¹⁾⁽²⁾	50-Ω resistor pull-up OUTx_PWR = 31	f_OUT = 8 GHz		2		dBm
p_OUT	Single-ended output power⁽¹⁾⁽²⁾	50-Ω resistor pull-up OUTx_PWR = 31	f_OUT = 15 GHz		0		dBm
INPUT SIGNAL PATH
f_OSC	Reference input frequency	OSC_2X = 0		5		1000	MHz
f_OSC	Reference input frequency	OSC_2X = 1		5		200	MHz
V_OSC	Reference input voltage⁽³⁾	f_OSC ≥ 20 MHz		0.4		2	V_PP
		10 MHz ≤ f_OSC < 20 MHz		0.8		2
		5 MHz ≤ f_OSC < 10 MHz		1.6		2
PHASE DETECTOR AND CHARGE PUMP
f_PD	Phase detector frequency⁽⁴⁾	MASH_ORDER = 0		0.125		250	MHz
f_PD	Phase detector frequency⁽⁴⁾	MASH_ORDER > 0		5		200	MHz
I_CPOUT	Charge-pump leakage current	CPG = 0			20		nA
I_CPOUT	Effective charge pump current	Sum of the up and down currents		3		15	mA
PN_{PLL_1/f}	Normalized PLL 1/f noise	f_PD = 100 MHz; f_VCO = 12 GHz⁽⁵⁾			–129		dBc/Hz
PN_{PLL_FOM}	Normalized PLL noise floor	f_PD = 100 MHz; f_VCO = 12 GHz⁽⁵⁾			–236		dBc/Hz
VCO CHARACTERISTICS
f_VCO	VCO frequency			7550		15100	MHz
PN_VCO	VCO phase noise	VCO1 f_VCO = 8.1 GHz	100 kHz		–106.5		dBc/Hz
			1 MHz		–128
			10 MHz		–147.5
			100 MHz		–154
		VCO2 f_VCO = 9.3 GHz	100 kHz		–105
			1 MHz		–126.5
			10 MHz		–146.5
			100 MHz		–154
		VCO3 f_VCO = 10.4 GHz	100 kHz		–103.5
			1 MHz		–125.5
			10 MHz		–146
			100 MHz		–158
		VCO4 f_VCO = 11.4 GHz	100 kHz		–102.5
			1 MHz		–124.5
			10 MHz		–145
			100 MHz		–160
		VCO5 f_VCO = 12.5 GHz	100 kHz		–100.5
			1 MHz		–122.5
			10 MHz		–143.5
			100 MHz		–154.5
		VCO6 f_VCO = 13.6 GHz	100 kHz		–99.5
			1 MHz		–122
			10 MHz		–142.5
			100 MHz		–154
		VCO7 f_VCO = 14.7 GHz	100 kHz		–98
			1 MHz		–120.5
			10 MHz		–141.5
			100 MHz		–155
t_VCOCAL	VCO calibration time⁽⁶⁾	Switch across the entire frequency band; f_OSC = f_PD = 100 MHz; VCO_SEL = 7			650		μs
K_VCO	VCO Gain	8.1 GHz			94		MHz/V
		9.3 GHz			106
		10.4 GHz			122
		11.4 GHz			148
		12.5 GHz			185
		13.6 GHz			202
		14.7 GHz			233
\|ΔT_CL\|	Allowable temperature drift	VCO not being re-calibrated			125		°C
H2	VCO second harmonic	f_VCO = 8 GHz; divider disabled			–30		dBc
H3	VCO third harmonic	f_VCO = 8 GHz; divider disabled			–25		dBc
DIGITAL INTERFACE
V_IH	High-level input voltage			1.4			V
V_IL	Low-level input voltage					0.4	V
I_IH	High-level input current			–100		100	μA
I_IL	Low-level input current			–100		100	μA
V_OH	High-level output voltage	Load current = –5 mA	MUXOUT pin	V_CC – 0.6			V
V_OL	High-level output current	Load current = 5 mA	MUXOUT pin			0.6	V

(1) Single ended output power obtained after de-embedding microstrip trace losses and matching with a manual tuner. Unused port terminated to 50-? load.

(2) Output power, spurs, and harmonics can vary based on board layout and components.

(3) Single-ended AC coupled sine wave input with complementary side AC coupled to ground with 50-? resistor.

(4) For lower VCO frequencies, the N divider minimum value can limit the phase-detector frequency.

(5) The PLL noise contribution is measured using a clean reference and a wide loop bandwidth and is composed into flicker and flat components. PLL_flat = PLL_FOM + 20 x log(f_VCO/f_PD) + 10 x log(f_PD/1 Hz). PLL_flicker (offset) = PLL_1/f + 20 x log(f_VCO/1 GHz) - 10 x log(offset/10 kHz). Once these two components are found, the total PLL noise can be calculated as PLL_Noise = 10 x log(10^PLL_Flat/10 + 10^{PLL_flicker/10}).

(6) See Section 7.3.7.1 for details.