亚洲一线二线三线写真,亚洲欧美国产国产综合一区,欠久久久久久久久久久免费视频

SNAS187D February 2003 – January 2016 LMX2430 , LMX2433 , LMX2434

PRODUCTION DATA.

封裝選項

機械數據 (封裝 | 引腳)

PW|20
- MPDS362A
NPE|20
- MPLG058

散熱焊盤機械數據 (封裝 | 引腳)

訂購信息

6 Pin Configuration and Functions

NPE Package

20-Pin ULGA Ultra Thin Chip Scale

Top View

PW Package

20-Pin TSSOP Thin Shrink Small Outline

Top View

Pin Functions

PIN			I/O	DESCRIPTION
NAME	ULGA	TSSOP	I/O	DESCRIPTION
CLK	18	19	I	MICROWIRE Clock input. High-impedance CMOS input. DATA is clocked into the 24-bit shift register on the rising edge of CLK.
CPoutIF	4	5	O	IF PLL charge-pump output. The output is connected to the external loop filter, which drives the input of the IF VCO.
CPoutRF	12	13	O	RF PLL charge-pump output. The output is connected to the external loop filter, which drives the input of the RF VCO.
DATA	19	20	I	MICROWIRE Data input. High-impedance CMOS input. Binary serial data. The MSB of DATA is shifted in first. The two last bits are the control bits.
EN	3	4	I	Chip Enable input. High-Impedance CMOS input. When this pin is set HIGH, the RF and IF PLLs are powered up. Power down is then controlled through the MICROWIRE. When this pin is set LOW, the device is asynchronously powered down, and the charge-pump output is forced to a high-impedance state (tri-state).
ENosc	5	6	I	Oscillator Enable input. High-impedance CMOS input. When this pin is set HIGH, the oscillator buffer is always powered up, independent of the state of the EN pin. When this pin is set LOW, the OSCout/ FLoutIF pin functions as an IF fastlock output, which connects a resistor in parallel to R2 of the external loop filter.
FinIF	2	3	I	IF PLL prescaler input. Small signal input from the VCO.
FLoutRF	10	11	O	RF PLL fastlock output. This pin connects a resistor in parallel to R2 of the external loop filter. This pin can also function as a general-purpose CMOS tri-state output.
FinRF	14	15	I	RF PLL prescaler input. Small-signal input from the VCO.
FinRF*	15	16	I	RF PLL prescaler complementary input. For single-ended operation, this pin must be AC grounded through a 100-pF capacitor. The LMX243x can be driven differentially when the AC-coupled capacitor is omitted.
Ftest/LD	9	10	O	Programmable multiplexed output. Functions as a general-purpose CMOS tri-state output, N and R divider output, RF/ IF PLL push-pull analog lock-detect output, RF/ IF PLL open-drain analog lock-detect output, or RF/ IF PLL digital filtered lock-detect output.
GND	1	2	—	Ground for the IF PLL analog and digital circuits, MICROWIRE, Ftest/LD and oscillator circuits.
	11	12
	13	14
LE	17	18	I	MICROWIRE Latch Enable input. High-impedance CMOS input. When LE transitions HIGH, DATA stored in the shift register is loaded into one of 6 internal control registers.
OSCout/ FLoutIF	6	7	O	Oscillator output/ IF PLL fastlock output. The output configuration is dependent on the state of the ENosc pin. When ENosc is set LOW, the pin functions as an IF fastlock output, which connects a resistor in parallel to R2 of the external loop filter. This configuration also functions as a general-purpose CMOS tri-state output. When ENosc is set HIGH, the pin functions as an oscillator output so that an external crystal can be used.
OSCin	7	8	I	Reference oscillator input. The input has an approximate Vcc/2 threshold and is driven by an external AC-coupled source.
Vcc	16	17	—	Power supply bias for the RF PLL analog circuits. Vcc may range from 2.25 V to 2.75 V. Bypass capacitors must be placed as close as possible to this pin and be connected directly to the ground plane.
	8	9
	20	1