The PCB layout of a DC-DC converter is critical for optimal performance of the application. For a buck converter the input loop formed by the input capacitors and power grounds are very critical. The input loop carries fast transient currents that cause larger transient voltages when reacting with a parasitic loop inductance. The IC uses two input loops in parallel IN1 and IN2 as shown in Figure 11-1 that cuts the parasitic input inductance in half. To get the minimum input loop area two small high frequency capacitors CIN1 and CIN2 are placed as close as possible.

To further reduce inductance, an input current return path should be placed underneath the loops IN1 and IN2. The closest metal plane is MID1 Layer2, and there is a solid copper plane placed right under the IN1 and IN2 loop the parasitic loop inductance is minimized. Connecting this MID1 Layer2 plane to GND provides a nice bridge connection between GND1 and GND2 as well. Minimizing the parasitic input loop inductance will minimize switch node ringing and EMI.

The output current loop can be optimized as well by using two ceramic output caps COUT1 and COUT2, one on each side. They form two parallel ground return paths OUT1 from COUT1 back to the low-side FET PGND1 pins 5, 6, 7, 8, and a second symmetric ground return path OUT2 from COUT2 back to low-side FET PGND2 pins 10, 11, 12, and 13. Having two parallel ground return paths yield reduced ground bouncing and reduced sensitivity of surrounding circuits.

Figure 11-1 Layout of the Power Components and Current Flow

Providing adequate thermal paths to dissipate heat is critical for operation at full current. The recommended method for heat dissipation is to use large solid 2-oz copper planes well connected to the power pins VIN1, VIN2, GND1, and GND2 which transfer the heat out of the IC over the TOP Layer1 copper planes. It is important to leave the TOP Layer1 copper planes as unbroken as possible so that heat is not trapped near the IC. The heat flow can be further optimized by thermally connecting the TOP Layer1 plane to large BOTTOM Layer 4 2-oz copper planes with vias. MID2 Layer3 is then open for all other signal routing. A fully filled or solid BOTTOM Layer4 ground plane without any interruptions or ground splitting is beneficial for EMI as well. Most important for low EMI is to use the smallest possible switch node copper area. The switch node including the C_BOOT cap has the largest dV/dt signal causing common-mode noise coupling. Using any kind of grounded shield around the switch node shortens and reduces this e-field.

All these DC-DC converter descriptions can be transformed into layout guidelines:

1. Place two 0.047-μF, 50-V high frequency input capacitors C_IN1 and C_IN2 as close as possible to the VIN1, VIN2, PGND1, PGND2 pins to minimize switch node ringing.
2. Place bypass capacitors for VCC and BIAS close to their respective pins. Make sure AGND pin sees the C_VCC and C_BIAS capacitors first before a connection to PGND.
3. Place C_BOOT capacitor with smallest parasitic loop. Shielding the C_BOOT capacitor and switch node has the biggest impact to reduce common-mode noise. Placing a small R_BOOT resistor (less than 3 Ω is recommended) in series to C_BOOT slows down the dV/dt of the switch node and reduce EMI.
4. Place the feedback resistor divider for adjustable parts as close as possible to the FB pin and to AGND pin of the device. Use a dedicated feedback trace, and route away from switch node and C_BOOT capacitor to avoid any cross coupling into sensitive analog feedback.
5. Use a dedicated BIAS trace to avoid noise into feedback trace.
6. Use a 3-Ω to 5-Ω resistor between the output and BIAS if the load is far from the output of the converter or inductive shorts on the output are possible.
7. Use well connected large 2-oz. TOP and BOTTOM copper planes for all power pins VIN1/2 and PGND1/2.
8. Minimize switch node and C_BOOT area for lowest EMI common mode noise.
9. Place input and output wires on the same side of the PCB using an EMI filter and away from the switch node for lowest EMI.

The resources in Section 12 provide additional important guidelines.