ZHCSJY0B June 2012 – June 2019 LMR12015 , LMR12020
PRODUCTION DATA.
| PIN | DESCRIPTION | |
|---|---|---|
| NO. | NAME | |
| 1,2 | SW | Output switch. Connects to the inductor, catch diode, and bootstrap capacitor. |
| 3 | BOOST | Boost voltage that drives the internal NMOS control switch. A bootstrap capacitor is connected between the BOOST and SW pins. |
| 4 | EN | Enable control input. Logic high enables operation. Do not allow this pin to float or be greater than VIN + 0.3 V. |
| 5 | SYNC | Frequency synchronization input. Drive this pin with an external clock or pulse train. Ground it to use the internal clock. |
| 6 | FB | Feedback pin. Connect FB to the external resistor divider to set output voltage. |
| 7 | GND | Signal and Power Ground pin. Place the bottom resistor of the feedback network as close as possible to this pin for accurate regulation. |
| 8 | AVIN | Supply voltage for the control circuitry. |
| 9,10 | PVIN | Supply voltage for output power stage. Connect a bypass capacitor to this pin. |
| DAP | GND | Signal / Power Ground and thermal connection. Tie this directly to GND (pin 7). See regarding optimum thermal layout. |