ZHCSFA1C June 2016 – November 2017 LMK60A0-148351 , LMK60A0-148M , LMK60E0-156257 , LMK60E2-150M
PRODUCTION DATA.
- 1 特性
- 2 應用
- 3 說明
- 4 修訂歷史記錄
- 5 Pin Configuration and Functions
-
6 Specifications
- 6.1 Absolute Maximum Ratings
- 6.2 ESD Ratings
- 6.3 Recommended Operating Conditions
- 6.4 Thermal Information
- 6.5 Electrical Characteristics - Power Supply
- 6.6 LVPECL Output Characteristics
- 6.7 LVDS Output Characteristics
- 6.8 HCSL Output Characteristics
- 6.9 OE Input Characteristics
- 6.10 Frequency Tolerance Characteristics
- 6.11 Power-On/Reset Characteristics (VDD)
- 6.12 PSRR Characteristics
- 6.13 PLL Clock Output Jitter Characteristics
- 6.14 Additional Reliability and Qualification
- 6.15 Typical Characteristics
- 7 Parameter Measurement Information
- 8 Power Supply Recommendations
- 9 Layout
- 10器件和文檔支持
- 11機械、封裝和可訂購信息
9.1.2 Best Practices for Signal Integrity
For best electrical performance and signal integrity of entire system with LMK60XX, TI recommends routing vias into decoupling capacitors and then into the LMK60XX. TI also recommends increasing the via count and width of the traces wherever possible. These steps ensure lowest impedance and shortest path for high-frequency current flow. Figure 12 shows the layout recommendation for LMK60XX.
Figure 12. LMK60XX Layout Recommendation for Power Supply and Ground