10.2.2 Detailed Design Procedure
Design of all aspects of the LMK04610 are quite involved and software has been written to assist in part selection and part programming. Contact TI for optimized loop filter settings based on the system requirement. This design procedure gives a quick outline of the process.
NOTE
This information is current as of the date of the release of this data sheet. Design tools receive continuous improvements to add features and improve model accuracy. Refer to software instructions or training for latest features.
- Device Selection
- The key to device selection is required VCO frequency given required output frequencies. The device must be able to produce the VCO frequency that can be divided down to required output frequencies.
- The software design tools take the VCO frequency range into account for specific devices based on the application's required output frequencies.
- To understand the process better, see the Detailed Description which provides more insight into the functional blocks and programming options.
- Device Configuration
There are many possible permutations of dividers and other registers to get same input and output frequencies from a device. However, consider that there are some optimizations and trade-offs. It is possible, although not assured, that some crosstalk and mixing could be created when using some divides.
- The optimum setting attempts to maximize phase detector frequency and uses the smallest dividers settings.
- For lowest possible in-band PLL noise, maximize phase detector frequency to minimize N divide value.
- As rule of thumb, keeping the phase detector frequency approximately between 10 × PLL loop bandwidth and 100 × PLL loop bandwidth. A phase detector frequency less than 5 × PLL bandwidth may be unstable and a phase detector frequency > 100 × loop bandwidth may experience increased lock time due to cycle slipping. However, for clock generation and jitter cleaning applications, lock time is typically not critical and large phase detector frequencies typically result in reduced PLL noise, so cycle-slipping during lock is acceptable.