SNOSA35G August 2002 – July 2015 LMH6657 , LMH6658
PRODUCTION DATA.
10 Layout
10.1 Layout Guidelines
Generally, a good high frequency layout will keep power supply and ground traces away from the inverting input and output pins. Parasitic capacitances on these nodes to ground will cause frequency response peaking and possible circuit oscillations. See Application Note OA-15, Frequent Faux Pas in Applying Wideband Current Feedback Amplifiers (SNOA367) for more information. TI suggests the following evaluation boards as a guide for high frequency layout and as an aid in device testing and characterization:
Table 1. Evaluation Board Guide
| DEVICE | PACKAGE | EVALUATION BOARD PIN | ||
|---|---|---|---|---|
| LMH6657MF | SOT-23-5 | LMH730216 | ||
| LMH6657MG | SC-70 | LMH730165 | ||
| LMH6658MA | 8-Pin SOIC | LMH730036 | ||
| LMH6658MM | 8-Pin VSSOP | LMH730123 | ||
Another important parameter in working with high speed/high performance amplifiers, is the component values selection. Choosing external resistors that are large in value will effect the closed loop behavior of the stage because of the interaction of these resistors with parasitic capacitances. These capacitors could be inherent to the device or a by-product of the board layout and component placement. Either way, keeping the resistor values lower, will diminish this interaction to a large extent. On the other hand, choosing very low value resistors will load down nodes and will contribute to higher overall power dissipation.
10.2 Layout Example
