ZHCSDJ6E February 2015 – June 2018 LMH1218
PRODUCTION DATA.
- 1 特性
- 2 應用
- 3 說明
- 4 修訂歷史記錄
- 5 Pin Configuration and Functions
- 6 Specifications
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3
Feature Description
- 7.3.1 Loss of Signal Detector
- 7.3.2 Continuous Time Linear Equalizer (CTLE)
- 7.3.3 2:1 Multiplexer
- 7.3.4 Clock and Data Recovery
- 7.3.5 Eye Opening Monitor (EOM)
- 7.3.6 Fast EOM
- 7.3.7 LMH1218 Device Configuration
- 7.3.8 Power-On Reset
- 7.4 Device Functional Modes
- 7.5 Programming
- 7.6 Register Maps
- 8 Application and Implementation
- 9 Power Supply Recommendations
- 10Layout
- 11器件和文檔支持
- 12機械、封裝和可訂購信息
5 Pin Configuration and Functions
RTW Package
24-Pin WQFN
(Top View)
Pin Descriptions – SPI Mode/ Mode_SEL = 1 kΩ to VDD
| PIN | TYPE | DESCRIPTION | |
|---|---|---|---|
| NAME | NO. | ||
| CONTROL/INDICATOR I/O | |||
| ENABLE | 6 | Input, 4-Level | Powers down device when pulled low
1 kΩ to VDD:
Float(Default):
20 kΩ to GND:
1 kΩ to GND:
|
| LOCK | 16 | Output, 2.5-V LVCMOS, 2-Level | Indicates CDR lock detect status
High:
Low:
|
| LOS_INT_N | 13 | Output,
LVCMOS Open-Drain, 2-Level |
Programmable Interrupt caused by change in LOS, violation of internal eye monitor threshold, or change in lock. External 4.7-kΩ pullup resistor is required. This pin is 3.3-V LVCMOS tolerant. |
| MISO | 15 | Output, 2.5-V LVCMOS, 2-Level | SPI Master Input / Slave Output. LMH1218 SPI data transmit |
| MODE_SEL | 1 | Input, 4-Level | Determines Device Configuration: SPI or SMBus
1 kΩ to VDD:
|
| MOSI | 4 | Input, 2-Level | SPI Master Output / Slave Input. LMH1218 SPI data receive |
| RESERVED | 5, 17, 18 | — | No Connect |
| SCK | 3 | Input, 2.5V LVCMOS, 2-Level | SPI serial clock input |
| SMPTE_10GbE | 14 | — | No Connect |
| SS_N | 2 | Input, 2-Level | SPI Slave Select. This pin has internal pullup |
| HIGH-SPEED DIFFERENTIAL I/O | |||
| IN0+ | 11 | Input, Analog | Inverting and noninverting differential inputs. An on-chip 100-Ω terminating resistor connects IN0+ to IN0-. Inputs require 4.7-µF, AC-coupling capacitors. |
| IN0– | 12 | Input, Analog | |
| IN1+ | 8 | Input, Analog | Inverting and noninverting differential inputs. An on-chip 100-Ω terminating resistor connects IN1+ to IN1-. Inputs require 4.7-µF, AC-coupling capacitors. |
| IN1– | 9 | Input, Analog | |
| OUT0+ | 20 | Output, 75-Ω CML Compatible | Inverting and noninverting 75-Ω outputs. An on-chip 75-Ω terminating resistor connects OUT0+ and OUT0- to VDD. Outputs require 4.7-µF, AC-coupling capacitors |
| OUT0– | 19 | Output, 75-Ω CML Compatible | |
| OUT1+ | 23 | Output, Analog | Inverting and noninverting differential outputs. An on-chip 100-Ω terminating resistor connects OUT1+ to OUT1-. Outputs require 4.7-µF, AC-coupling capacitors |
| OUT1– | 22 | Output, Analog | |
| POWER | |||
| DAP | — | Ground | Exposed DAP, connect to GND using at least 5 vias (see package drawing) |
| VDD | 7, 21 | 2.5-V Supply | 2.5 V ± 5% |
| VSS | 10, 24 | Ground | Ground |
Pin Descriptions – SMBUS Mode/ MODE_SEL = 1 kΩ to GND
| PIN | TYPE | DESCRIPTION | |
|---|---|---|---|
| NAME | NO. | ||
| ADDR0 | 2 | Input, 4-Level | 4-level strap pins used to set the SMBus address of the device. The pin state is read on power-up. The multi-level nature of these pins allows for 16 unique device addresses. Note the SMBus section for further details. The four strap options include:
1 kΩ to VDD:
Float(Default): Represents logic state 10'b 7-bits SMBus address = 0x17 20 kΩ to GND:
1 kΩ to GND:
|
| ADDR1 | 15 | ||
| ENABLE | 6 | Input, 4-Level | Powers down device when pulled low
1 kΩ to VDD:
Float(Default): Reserved 20 kΩ to GND:
1 kΩ to GND:
|
| LOCK | 16 | Output, 2.5-V LVCMOS, 2-Level | Indicates CDR lock Status
High:
Low:
|
| LOS_INT_N | 13 | Output, LVCMOS
Open-Drain, 2-Level |
Programmable Interrupt caused by change in LOS, violation of internal eye monitor threshold, change in lock. External 4.7-kΩ pullup resistor is required. This pin is 3.3-V LVCMOS tolerant. |
| MODE_SEL | 1 | Input, 4-Level | Determines Device Configuration: SPI or SMBus
1 kΩ to GND: SMBUS mode. See Initialization Set Up |
| RESERVED | 5, 17, 18 | — | No Connect |
| SCL | 3 | Input, 2-Level | SMBus clock input / open-drain. External 2-kΩ to 5-kΩ pullup resistor is required as per SMBus interface standard. This pin is 3.3-V LVCMOS tolerant. |
| SDA | 4 | I/O, Open-Drain, 2-Level | SMBus data input / open-drain. External 2-kΩ to 5-kΩ pullup resistor is required as per SMBus interface standard. This pin is 3.3-V LVCMOS tolerant. |
| SMPTE_10GbE | 14 | No Connect | |
| HIGH-SPEED DIFFERENTIAL I/O | |||
| DAP | — | Ground | Exposed DAP, connect to GND using at least 5 vias (see package drawing) |
| IN0+ | 11 | Input, Analog | Inverting and noninverting differential inputs. An on-chip 100-Ω terminating resistor connects IN0+ to IN0–. Inputs require 4.7-µF, AC-coupling capacitors. |
| IN0– | 12 | Input, Analog | |
| IN1+ | 8 | Input, Analog | Inverting and noninverting differential inputs. An on-chip 100-Ω terminating resistor connects IN0+ to IN0–. Inputs require 4.7-µF, AC-coupling capacitors. |
| IN1– | 9 | Input, Analog | |
| OUT0+ | 20 | Output, 75-Ω CML Compatible | Inverting and noninverting 75-Ω outputs. An on-chip 75-Ω terminating resistor connects OUT0+ and OUT0– to VDD. Outputs require 4.7-µF, AC-coupling capacitors |
| OUT0– | 19 | Output, 75-Ω CML Compatible | |
| OUT1+ | 23 | Output, Analog | Inverting and noninverting differential outputs. An on-chip 100 Ω terminating resistor connects OUT1+ to OUT1–. Outputs require 4.7-µF, AC-coupling capacitors |
| OUT1– | 22 | Output, Analog | |
| VDD | 7, 21 | 2.5-V Supply | 2.5 V ± 5% |
| VSS | 10, 24 | Ground | Ground |