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ZHCSDJ6E February 2015 – June 2018 LMH1218

PRODUCTION DATA.

封裝選項

機械數據 (封裝 | 引腳)

RTW|24
- MPQF167C

散熱焊盤機械數據 (封裝 | 引腳)

RTW|24
- QFND450A

訂購信息

6.5 Electrical Characteristics

Over operating free-air temperature range (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
POWER
PD	Power dissipation	Locked 75 Ω OUT0 only (800 mVpp), EOM powered down		300		mW
		Locked OUT1 only (600 mVpp, diff), EOM powered down		195		mW
		Transient power during CDR lock acquisition, 75 Ω OUT0 and OUT1 powered up, EOM powered down		400	500	mW
PD_RAW	Power dissipation in force RAW mode (CDR bypass)	EQ bypass, OUT0 720mVpp, OUT1 600mVpp IN0 to OUT0 and OUT1 or IN1 to OUT0 and OUT1		195		mW
		IN0 to OUT0, OUT1 powered down		160		mW
		IN1 to OUT1, OUT0 powered down		80		mW
4-LEVEL INPUT AND 2.5 V LVCMOS DC SPECIFICATIONS
V_IH	High level input voltage	4-level input (MODE_SEL, ADDR0/1, ENABLE pins)		0.95 × VDD		V
V_IF	Float level input voltage	4-level input (MODE_SEL, ADDR0/1, ENABLE pins)		0.67 × VDD		V
V_I20K	20K to GND input voltage	4-level input (MODE_SEL, ADDR0/1, ENABLE pins)		0.33 × VDD		V
V_IL	Low level input voltage	4-level input (MODE_SEL, ADDR0/1, ENABLE pins)		0.1		V
V_OH	High level output voltage	IOH = -3 mA	2			V
V_OL	Low level output voltage	IOL = 3 mA			0.4	V
I_IH	Input high leakage current	V_input= VDD SPI Mode: LVCMOS (SPI_SCK, SPI_SS_N) pins			15	µA
		SMBus Mode: LVCMOS (SMB_SDA, SMB_SCL) pins			15	µA
		SMBus Mode: 4-Levels (ADDR0, ADDR1) pins	20	44	80	µA
		4-Levels (MODE_SEL, ENABLE) pins	20	44	80	µA
I_IL	Input low leakage current	Vinput = GND SPI Mode: LVCMOS (SPI_MOSI, SPI_SCK) pins	–15			µA
		Vinput = GND SPI Mode: LVCMOS (SPI_SS_N) pins	–37			µA
		SMBus Mode: LVCMOS (SMB_SDA, SMB_SCL pins	–15			µA
		SMBus Mode: 4-Levels (ADDR0, ADDR1) pins	–160	–93	–40	µA
		4-Levels (MODE_SEL, ENABLE) pins	–160	–93	–40	µA
3.3-V TOLERANT LVCMOS / LVTTL DC SPECIFICATIONS (SDA, SCL, LOS_INT_N)
V_IH25	High level input voltage	2.5-V Supply Voltage	1.75		3.6	V
V_IL	Low level input voltage		GND		0.8	V
V_OL	Low level output voltage	IOL = 1.25 mA			0.4	V
I_IH	Input high current	VIN = 2.5 V, VDD = 2.5 V	20		40	μA
I_IL	Input low current	VIN = GND, VDD = 2.5 V	-10		10	μA
SIGNALDETECT
S_DH	Signal detect (default) Assert threshold level⁽²⁾⁽³⁾	11.88 Gbps, SMPTE (EQ, PLL) Pathological Pattern		26		mV_P-P
		10.3125 Gbps, 1010 Clock Pattern, no media		30		mV_P-P
		10.3125 Gbps, PRBS31 Pattern		21		mV_P-P
S_DL	Signal detect (default) De-assert threshold level⁽²⁾	11.88 Gbps, SMPTE (EQ, PLL) Pathological Patterns		20		mV_P-P
		10.3125 Gbps, 1010 Clock Pattern		15		mV_P-P
		10.3125 Gbps, PRBS31 Pattern		12		mV_P-P
HIGH-SPEED RECEIVE RX INPUTS (IN_n+, IN_n–)
R_RD	DC Input differential resistance		75	100	125	Ω
RL_RX-SDD	Input differential return loss⁽¹⁾	Measured with the device powered up. SDD11 10 MHz to 2 GHz		–14		dB
		SDD11 2 GHz to 6 GHz		–6.5		dB
		SDD11 6 GHz to 12 GHz		–6.5		dB
RL_RX-SCD	Differential to common mode Input conversion⁽¹⁾	Measure with the device powered up.SCD11, 10 MHz to 12 GHz		–20		dB
HIGH-SPEED OUTPUTS (OUT_n+, OUT_n–)
V_{VOD_OUT1}	Output differential voltage⁽¹⁾⁽⁵⁾	Default setting, 8T clock pattern	400	600	700	mV_P-P
V_{VOD_OUT1_DE}	De-emphasis Level	VOD = 600 mV, maximum De-Emphasis with 16T clock pattern		–9		dB
V_{VOD_OUT1_CLK}	Clock output differential voltage	2.97 GHz,1.485 GHz, 297 MHz, and 270 MHz		560		mV_P-P
V_{VOD_OUT0}	Output single ended voltage at OUT0+ with OUT0– terminated⁽¹⁾⁽⁵⁾⁽⁹⁾	Default setting	720	778	880	mV_P-P
R_{DIFF_OUT1}	DC output differential resistance			100		Ω
R_{DIFF_OUT0}	DC output single-ended resistance			75		Ω
T_{R_F_OUT1}	Output rise/fall time	Full Slew Rate, 20% to 80% using 8T Pattern		45		ps
T_{R_F_OUT0}	Output rise/fall time, PRBS10⁽¹⁾⁽⁵⁾	11.88 Gbps		35	45	ps
		5.94 Gbps		35	45	ps
		2.97 Gbps		35	45	ps
		1.485 Gbps		35	45	ps
		270 Mbps	400	950	1500	ps
T_{R_F_OUT0_delta}	Output rise/fall time mismatch⁽¹⁾⁽⁵⁾	11.88 Gbps		3	18	ps
		5.94 Gbps		3	18	ps
		2.97 Gbps		3	18	ps
		1.485 Gbps		3	18	ps
		270 Mbps		72	500	ps
V_{OVR_UDR_SHOOT}	Output overshoot, undershoot⁽¹⁾⁽⁵⁾	12G/6G/3G/HD/SD Measured with 8T pattern		2.4%	3.4%
V_{DC_OFFSET}	DC offset⁽¹⁾	12G/6G/3G/HD/SD		±0.2		V
V_{DC_WANDER}	DC wander⁽¹⁾	12G/6G/3G/HD/SD EQ Pathological		20		mV
RL_{OUT0_S22}	OUT0 single-ended 75-Ω return loss⁽¹⁾⁽⁵⁾⁽⁷⁾	S22 5 MHz to 1.485 GHz		< –15		dB
		S22 1.485 GHz to 3 GHz		< –10		dB
		S22 3 GHz to 6 GHz		< –7		dB
		S22 6 GHz to 12 GHz		< –4		dB
RL_{OUT1_SDD22}	OUT1 differential 100-Ω return loss⁽¹⁾⁽⁵⁾⁽⁶⁾	SDD22 10 MHz - 2 GHz		–20		dB
		SDD22 2 GHz - 6 GHz		–17		dB
		SDD22 6 GHz - 11.1 GHz		–14		dB
RL_{OUT1_SCC22}	OUT1 common-mode 50-Ω return loss⁽¹⁾⁽⁵⁾⁽⁶⁾	SCC22 10 MHz - 4.75 GHz		–11		dB
RL_{OUT1_SCC22}	OUT1 common-mode 50-Ω return loss⁽¹⁾⁽⁵⁾⁽⁶⁾	SCC22 4.75 GHz - 11.1 GHz		–12		dB
V_{VCM_OUT1_NOISE}	AC common-mode voltage noise⁽¹⁾⁽⁵⁾	VOD = 0.6 Vpp, DE = 0dB, PRBS31, 10.3125 Gbps		8		mV_RMS
T_{RCK_LATENCY}	Latency reclocked	Reclocked Data		1.5 UI +195		ps
T_{RAW_LATENCY}	Latency CDR bypass	Raw Data		230		ps
TRANSMIT OUTPUT JITTER SPECIFICATIONS
A_{J_OUT0}	Alignment jitter⁽¹⁾⁽⁵⁾	OUT0, PRBS15, 11.88 Gbps		0.18		UI
T_{J_OUT1}	Total jitter (1E-12)⁽¹⁾⁽⁵⁾	OUT1, PRBS15 10.3125 Gbps		0.12		UI
R_{J_OUT1}	Random jitter (rms)	OUT1, PRBS15, 10.3125 Gbps		0.38		ps_RMS
D_{J_OUT1}	Deterministic jitter	OUT1, PRBS15, 10.3125 Gbps		7		ps_P-P
D_{J_OUT1_RAW}	Deterministic jitter	OUT1, RAW MODE (CDR bypass) PRBS15, 11.88 Gbps, 35 inch FR4 trace, EQ=0x95, VID = 800mVpp		25		ps_P-P
CLOCK DATA RECOVERY
D_{DATA_RATE}		ST-2082 (proposed)⁽⁸⁾		11.88, 11.868		Gbps
		ST-2081 (proposed)⁽⁸⁾		5.94, 5.934		Gbps
		SMPTE 424⁽⁸⁾		2.97, 2.967		Gbps
		SMPTE 292⁽⁸⁾		1.485, 1.4835		Gbps
		SMPTE 259M⁽⁸⁾		270		Mbps
		10 GbE⁽⁸⁾		10.3125		Gbps
P_{PLL_BW}	PLL bandwidth at –3 dB	Measured with 0.2UI S_J at 10.3125 Gbps		8		MHz
		Measured with 0.2UI S_J at 11.88 Gbps		13		MHz
		Measured with 0.2UI S_J at 5.94 Gbps		7		MHz
		Measured with 0.2UI S_J at 2.97 Gbps		5		MHz
		Measured with 0.2UI S_J at 1.485 Gbps		3		MHz
		Measured with 0.2UI S_J at 270 Mbps		1		MHz
J_TOL	Total input jitter tolerance	TJ = D_J + R_J + S_J, D_J+R_J = 0.15 UI S_J/P_J, low to high upward sweep (10 kHz to 80 MHz)		0.65		UI
T_LOCK	Lock time⁽¹⁾⁽⁴⁾	From signal detected to the lock asserted, HEO/VEO lock monitor disable, same setting for 11.88G, 5.94G, 2.97G, 1.485G and 270-MHz data rates		<5		ms
T_{TEMP_LOCK}	CDR lock with temperature ramp	Temperature Lock Range, 5ºC per minute ramp up and down, –40ºC to 85ºC operating range		125		°C

(1) These limits are ensured by bench characterization and are not production tested.

(2) Data with extraordinarily long periods of high-frequency 1010 data, and for long, lossy channels, the signal amplitude at the input to the device may be severely attenuated by the channel and may fall below the signal detect assert and/or de-assert thresholds.

(3) The voltage noise on the receiver inputs which has an amplitude larger than the signal detect assert threshold may trigger a signal detect assert condition

(4) The total CDR lock time depends on number of rate settings enabled and application data rate

(5) Dependent on board layout. Characterization data was measured with LMH1218EVM evaluation board

(6) Measure with the device powered up and outputs a clock signal.

(7) Output return loss is dependent on board design, this is measured with the LMH1218EVM evaluation board

(8) Data rate tolerance is within ±1000 ppm

(9) ATE Production tested using DC method. Apply differential DC signal at the input and measure OUT0P amplitude. OUT0N terminated in 75 Ω.