SNLS312M August 2010 – July 2015 LMH0394
PRODUCTION DATA.
| MIN | MAX | UNIT | ||
|---|---|---|---|---|
| Supply voltage | 3.1 | V | ||
| Input voltage (all inputs) | –0.3 | VCC + 0.3 | V | |
| Junction temperature | 125 | °C | ||
| Storage temperature, Tstg | –65 | 150 | °C | |
| VALUE | UNIT | |||
|---|---|---|---|---|
| V(ESD) | Electrostatic discharge | Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±6000 | V |
| Charged-device model (CDM), per JEDEC specification JESD22-C101(2) | ±2000 | V | ||
| MIN | NOM | MAX | UNIT | |
|---|---|---|---|---|
| Supply voltage (VCC – VEE) | 2.375 | 2.5 | 2.625 | V |
| Input coupling capacitance | 1 | µF | ||
| Operating free-air temperature (TA) | –40 | 25 | 85 | °C |
| THERMAL METRIC(1) | LMH0394 | UNIT | |
|---|---|---|---|
| RUM (WQFN) | |||
| 16 PINS | |||
| RθJA | Junction-to-ambient thermal resistance | 40 | °C/W |
| RθJC(top) | Junction-to-case (top) thermal resistance | 6 | °C/W |
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| VIH | Input voltage high level | Logic inputs | 1.7 | VCC | V | |
| VIL | Input voltage low level | Logic inputs | VEE | 0.7 | V | |
| VSDI | Input voltage swing | 0m cable length(3) (SDI) | 720 | 800 | 880 | mVP−P |
| VCMIN | Input common-mode voltage | 1.65 | V | |||
| VSSP-P | Differential output voltage, P-P | 100-Ω load, default register settings, Figure 1(4) (SDO, SDO) | 500 | 700 | 900 | mVP-P |
| VOD | Differential output voltage | 250 | 350 | 450 | mV | |
| ΔVOD | Change in magnitude of VOD for complementary output states | 50 | mV | |||
| VOS | Offset voltage | 1.1 | 1.2 | 1.35 | V | |
| ΔVOS | Change in magnitude of VOS for complementary output states | 50 | mV | |||
| IOS | Output short circuit current | 30 | mA | |||
| MUTEREF | MUTEREF DC voltage (floating) | MUTEREF | 1.3 | V | ||
| MUTERNG | MUTEREF range | MUTEREF | 0.8 | V | ||
| VOH | Output voltage high level | IOH = -2 mA (CD, MISO) | 2.0 | V | ||
| VOL | Output voltage low level | IOL = +2 mA (CD, MISO) | 0.2 | V | ||
| ICC | Supply current | Normal operation(5) | 45 | 65 | mA | |
| Power-save mode | 7 | 10 | mA | |||
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| BRMIN | Minimum input data rate | SDI, SDI | 125 | Mbps | ||
| BRMAX | Maximum input data rate | SDI, SDI | 2970 | Mbps | ||
| TJRAW | Jitter for various cable lengths | 2.97 Gbps, Belden 1694A, 0-100 meters(2) |
0.2 | UI | ||
| 2.97 Gbps, Belden 1694A, 100-140 meters(2) |
0.3 | UI | ||||
| 2.97 Gbps, Belden 1694A, 140-180 meters(2) |
0.5 | UI | ||||
| 2.97 Gbps, Belden 1694A, 180-200 meters |
0.55 | UI | ||||
| 1.485 Gbps, Belden 1694A, 0-200 meters(2) |
0.2 | UI | ||||
| 1.485 Gbps, Belden 1694A, 200-220 meters |
0.3 | UI | ||||
| 270 Mbps, Belden 1694A, 0-400 meters(2) |
0.3 | UI | ||||
| tR, tF | Output rise time, fall time | SDO, SDO, 20% – 80%, and 100-Ω load Figure 1(3) | 90 | 130 | ps | |
| ΔTR_F | Mismatch in rise / fall time | SDO, SDO (3) | 2 | 15 | ps | |
| tOS | Output overshoot | SDO, SDO(3) | 1% | 5% | ||
| RLIN | Input return loss | 5 MHz - 1.5 GHz(4) SDI or SDI | 15 | dB | ||
| 1.5 GHz - 3.0 GHz(4) SDI or SDI | 10 | dB | ||||
| RIN | Input resistance | single-ended SDI or SDI | 1.5 | kΩ | ||
| CIN | Input capacitance | single-ended SDI or SDI | 0.7 | pF | ||
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| Recommended Input Timing Requirements | ||||||
| fSCK | SCK frequency | 20 | MHz | |||
| tPH | SCK pulse width high | See Figure 2 and Figure 3 | 40 | % SCK period | ||
| tPL | SCK pulse width low | 40 | % SCK period | |||
| tSU | MOSI set-up time | See Figure 2Figure 3 | 4 | ns | ||
| tH | MOSI hold time | 4 | ns | |||
| tSSSU | SS set-up time | See Figure 2 and Figure 3 | 14 | ns | ||
| tSSH | SS hold time | 4 | ns | |||
| tSSOF | SS OFF-time | 1 | SCK period | |||
| Switching Characteristics | ||||||
| tODZ | MISO driven-to-TRI-STATE time | See Figure 3 | 20 | ns | ||
| tOZD | MISO TRI-STATE-to-driven time | 10 | ns | |||
| tOD | MISO output delay time | 15 | ns | |||
Figure 1. LVDS Output Voltage, Offset, and Timing Parameters
Figure 2. SPI Write
Figure 3. SPI Read

