ZHCSJE7A March 2019 – September 2019 LM76202-Q1
PRODUCTION DATA.
The FLT open-drain output asserts (active low) under following conditions:
The FLT output does not assert in the event of reverse voltage on Input.
The device is designed to eliminate false reporting by using an internal "de-glitch" circuit for fault conditions without the need for an external circuitry.
The FLT signal can also be used as Power Good indicator to the downstream loads like DC-DC converters. An internal Power Good (PGOOD) signal is OR'd with the fault logic. During start-up, when the device is operating in dVdT mode, PGOOD and FLT remains low and is de-asserted after the dVdT mode is completed and the internal FET is fully enhanced and VOUT has reached VIN. The PGOOD signal has deglitch time incorporated to ensure that internal FET is fully enhanced before heavy load is applied by the downstream converters. Rising deglitch delay is determined by tPGOOD(degl) = Maximum {(900 + 20 × C(dVdT)), tPGOODR}, where C(dVdT) is in nF and tPGOOD(degl) is in µs. FLT can be left open or connected to RTN when not used. V(IN) falling below V(PORF) resets FLT.