ZHCSM29A September 2023 – June 2024 LM70840-Q1 , LM70860-Q1 , LM70880-Q1
PRODUCTION DATA
- 1
- 1 特性
- 2 應用
- 3 說明
- 4 說明（續）
- 5 Pin Configuration and Functions
- 6 Specifications
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3
Feature Description
- 7.3.1 Input Voltage Range (VIN)
- 7.3.2 High-Voltage Bias Supply Regulator (VCC, BIAS, VDDA)
- 7.3.3 Enable (EN)
- 7.3.4 Power-Good Monitor (PG)
- 7.3.5 Switching Frequency (RT)
- 7.3.6 Dual Random Spread Spectrum (DRSS)
- 7.3.7 Soft Start
- 7.3.8 Output Voltage Setpoint (FB)
- 7.3.9 Minimum Controllable On-Time
- 7.3.10 Error Amplifier and PWM Comparator (FB, EXTCOMP)
- 7.3.11 Slope Compensation
- 7.3.12 Shunt Current Sensing
- 7.3.13 Hiccup Mode Current Limiting
- 7.3.14 Device Configuration (CONFIG)
- 7.3.15 Single-Output Dual-phase Operation
- 7.3.16 Pulse Frequency Modulation (PFM) / Synchronization
- 7.3.17 Thermal Shutdown (TSD)
- 7.4 Device Functional Modes
-
8 Application and Implementation
- 8.1 Application Information
- 8.2
Typical Applications
- 8.2.1
Design 1 – High Efficiency, Wide Input, 400-kHz Synchronous
Buck Regulator
- 8.2.1.1 Design Requirements
- 8.2.1.2
Detailed Design Procedure
- 8.2.1.2.1 Custom Design With WEBENCH? Tools
- 8.2.1.2.2 Custom Design With Excel Quickstart Tool
- 8.2.1.2.3 Buck Inductor
- 8.2.1.2.4 Current-Sense Resistance
- 8.2.1.2.5 Output Capacitors
- 8.2.1.2.6 Input Capacitors
- 8.2.1.2.7 Frequency Set Resistor
- 8.2.1.2.8 Feedback Resistors
- 8.2.1.2.9 Compensation Components
- 8.2.1.3 Application Curves
- 8.2.2 Design 2 – High Efficiency 48V to 12V 400kHz Synchronous Buck Regulator
- 8.2.1
Design 1 – High Efficiency, Wide Input, 400-kHz Synchronous
Buck Regulator
- 8.3 Power Supply Recommendations
- 8.4 Layout
- 9 Device and Documentation Support
- 10Revision History
- 11Mechanical, Packaging, and Orderable Information
7.3.15 Single-Output Dual-phase Operation
For single-output, dual-phase operation, two LM708x0-Q1 devices are required. Additional phases cannot be added. Configure the first device as a primary and the second device as a secondary per Table 7-2. This action disables the feedback error amplifier of the secondary device and places it into a high-impedance state. Connect EXTCOMP pins of the primary and secondary devices together with minimal trace length. Add an external compensation network near the primary device. Internal compensation feature is not supported when operating in dual-phase configuration. The PG / SYNCOUT pin of the primary device must be connected to the PFM / SYNCIN pin of the secondary device. The SYNCOUT of the primary device is 180° out-of-phase and facilitates the interleaved operation. RT pin is not used for the oscillator when the LM708x0-Q1 is configured as a secondary device but instead is used for the slope compensation. RT resistance on the secondary device needs to be the same value as RT resistance on the primary device to make sure of correct operation. The oscillator frequency is derived from the primary device. When operating in Interleaved mode, both devices need to be enabled at the exact same time for start-up. After the regulator has started, pull the secondary EN pin low (< 0.8V) for phase shedding if needed at light load to increase the efficiency.
Configure PFM mode by connecting both the PFM/SYNC pin of the primary and the FB pin of the secondary to the VDDA pin as shown in Figure 7-6.
Figure 7-6 Simplified Schematic for Single-Output
Dual-Phase Operation in PFM ModeConfigure FPWM mode by applying an external synchronization signal to the PFM/SYNCIN pin of the primary or connecting the pin to the AGND and connecting the FB pin of the secondary to the AGND pin as shown in Figure 7-7.
Figure 7-7 Simplified Schematic for Single-Output Dual-Phase Operation in FPWM Mode
In PFM mode, while the primary device is pulse skipping to reduce the IQ-SLEEP current, the primary device disables the synchronization clock output, therefore the phase shedding is not supported. Phase shedding is only supported in FPWM.
When operating in PFM mode under light load conditions, either primary device or secondary device or both devices can switch.
In FPWM mode, the secondary device can be disabled to reduce the IQ-SLEEP current, and then the device can be enabled to support higher load currents when needed. When the secondary device enable is recycled the internal soft-start is pulled low, and then the LM708x0-Q1 goes through a normal soft-start turn-on. During the secondary soft-start time (2.8ms typical) there is a phase current imbalance until the soft-start is done. The phase current imbalance is also possible when in dropout as there is no control over the current. Matching the impedance of the outputs of the primary and secondary devices minimizes the phase current imbalance.
For more information, see Benefits of a Multiphase Buck Converter and Multiphase Buck Design From Start to Finish.