ZHCSKX9D May 2019 – July 2022 LM61460
PRODUCTION DATA
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| SUPPLY VOLTAGE AND CURRENT | ||||||
| VIN_OPERATE | Input operating voltage(2) | Needed to start up | 3.95 | V | ||
| Once operating | 3.0 | |||||
| VIN_OPERATE_H | Hysteresis(2) | 1 | V | |||
| IQ_VIN | Operating quiescent current (not switching) | VFB = +5%, VBIAS = 5 V | 9 | 18 | μA | |
| ISD | Shutdown quiescent current; measured at the VIN pin | EN = 0 V, TJ = 25℃ | 0.6 | 6 | μA | |
| ENABLE | ||||||
| VEN | Enable input threshold voltage – rising | 1.263 | V | |||
| VEN-ACC | Enable input threshold voltage – rising deviation from typical | –5% | 5% | |||
| VEN-HYST | Enable threshold hysteresis as percentage of VEN (typical) | 24% | 28% | 32% | ||
| VEN-WAKE | Enable wake-up threshold | 0.4 | V | |||
| IEN | Enable pin input current | VIN = EN = 13.5 V | 2.3 | nA | ||
| VEN_SYNC | Edge height necessary to sync using EN/SYNC pin | Rise/fall time < 30 ns | 2.4 | V | ||
| LDO - VCC | ||||||
| VCC | Internal VCC voltage | VBIAS > 3.4 V, CCM operation(2) | 3.3 | V | ||
| VBIAS = 3.1 V, non-switching | 3.1 | |||||
| VCC_UVLO | Internal VCC input undervoltage lockout | VCC rising undervoltage threshold | 3.6 | V | ||
| VCC_UVLO_HYST | Internal VCC input undervoltage lockout | Hysteresis below VCC_UVLO | 1.1 | V | ||
| FEEDBACK | ||||||
| VFB_acc | Initial reference voltage accuracy | VIN = 3.3 V to 36 V, FPWM mode | –1% | 1% | ||
| IFB | Input current from FB to AGND | Adjustable versions only, FB = 1 V | 10 | nA | ||
| OSCILLATOR | ||||||
| fADJ | Minimum adjustable frequency by RT or SYNC | RT = 66.5 k? | 0.18 | 0.2 | 0.22 | MHz |
| Adjustable frequency by RT or SYNC with 400-kHz setting | RT = 33.2 k? | 0.36 | 0.4 | 0.44 | MHz | |
| Maximum adjustable frequency by RT or SYNC | RT = 5.76 k? | 1.98 | 2.2 | 2.42 | MHz | |
| MOSFETS | ||||||
| RDS(ON)_HS | Power switch on-resistance | High-side MOSFET RDS(ON) | 41 | 82 | m? | |
| RDS(ON)_LS | Power switch on-resistance | Low-side MOSFET RDS(ON) | 21 | 45 | m? | |
| VBOOT_UVLO | Voltage on CBOOT pin compared to SW which will turn off high-side switch | 2.1 | V | |||
| CURRENT LIMITS | ||||||
| IL-HS | High-side switch current limit(1) | Duty cycle approaches 0% | 8.9 | 10.3 | 11.5 | A |
| IL-LS | Low-side switch current limit | 6.1 | 7.1 | 8.1 | A | |
| IL-ZC | Zero-cross current limit. Positive current direction is out of the SW pin | Auto mode, static measurement | 0.25 | A | ||
| IL-NEG | Negative current limit FPWM and SYNC Modes. Positive current direction is out of SW pin. | FPWM operation | –3 | A | ||
| IPK_MIN_0 | Minimum peak command in auto mode and device current rating | Pulse duration < 100 ns | 25% | |||
| IPK_MIN_100 | Minimum peak command in auto mode and device current rating | Pulse duration > 1 μs | 12.5% | |||
| VHICCUP | Ratio of FB voltage to in-regulation FB voltage | Not during soft start | 40% | |||
| POWER GOOD | ||||||
| PGDOV | PGOOD upper threshold – rising | % of VOUT setting | 105% | 107% | 110% | |
| PGDUV | PGOOD lower threshold – falling | % of VOUT setting | 92% | 94% | 96.5% | |
| PGDHYST | PGOOD upper threshold (rising and falling) | % of VOUT setting | 1.3% | |||
| VIN(PGD_VALID) | Input voltage for proper PGOOD function | 1.0 | V | |||
| VPGD(LOW) | Low level PGOOD function output voltage | 46-μA pullup to the PGOOD pin, VIN = 1.0 V, EN = 0 V | 0.4 | V | ||
| 1-mA pullup to the PGOOD pin, VIN = 13.5 V, EN = 0 V | 0.4 | |||||
| 2-mA pullup to the PGOOD pin, VIN = 13.5 V, EN = 3.3 V | 0.4 | |||||
| RPGD | RDS(ON) of PGOOD output | 1-mA pullup to PGOOD pin, EN = 0 V | 17 | 40 | ? | |
| 1-mA pullup to PGOOD pin, EN = 3.3 V | 40 | 90 | ? | |||
| IOV | Pulldown current at the SW node under overvoltage condition | 0.5 | mA | |||
| THERMAL SHUTDOWN | ||||||
| TSD_R | Thermal shutdown rising threshold(2) | 158 | 168 | 180 | ℃ | |
| TSD_HYST | Thermal shutdown hysteresis(2) | 10 | ℃ | |||