ZHCSL19C May 2019 – June 2021 LM61440
PRODUCTION DATA
- 1 特性
- 2 應用
- 3 說明
- 4 Revision History
- 5 Device Comparison Table
- 6 Pin Configuration and Functions
- 7 Specifications
-
8 Detailed Description
- 8.1 Overview
- 8.2 Functional Block Diagram
- 8.3
Feature Description
- 8.3.1 EN/SYNC Uses for Enable and VIN UVLO
- 8.3.2 EN/SYNC Pin Uses for Synchronization
- 8.3.3 Clock Locking
- 8.3.4 Adjustable Switching Frequency
- 8.3.5 PGOOD Output Operation
- 8.3.6 Internal LDO, VCC UVLO, and BIAS Input
- 8.3.7 Bootstrap Voltage and VCBOOT-UVLO (CBOOT Pin)
- 8.3.8 Adjustable SW Node Slew Rate
- 8.3.9 Spread Spectrum
- 8.3.10 Soft Start and Recovery From Dropout
- 8.3.11 Output Voltage Setting
- 8.3.12 Overcurrent and Short Circuit Protection
- 8.3.13 Thermal Shutdown
- 8.3.14 Input Supply Current
- 8.4 Device Functional Modes
- 9 Application and Implementation
- 10Power Supply Recommendations
- 11Layout
- 12Device and Documentation Support
- 13Mechanical, Packaging, and Orderable Information
8.4.3.2.2 Frequency Reduction
The LM61440 reduces frequency whenever output voltage is high. This function is enabled whenever Comp, an internal signal, is low and there is an offset between the regulation set point of FB and the voltage applied to FB. The net effect is that there is larger output impedance while lightly loaded in auto mode than in normal operation. Output voltage must be approximately 1% high when the part is completely unloaded.
In PFM operation, a small DC positive offset is required on the output voltage to activate the PFM detector. The lower the frequency in PFM, the more DC offset is needed on VOUT. If the DC offset on VOUT is not acceptable, a dummy load at VOUT or FPWM Mode can be used to reduce or eliminate this offset.