ZHCSEX5 April 2016 LM5175-Q1
PRODUCTION DATA.
- 1 特性
- 2 應(yīng)用
- 3 說明
- 4 簡化電路原理圖
- 5 修訂歷史記錄
- 6 Pin Configuration and Functions
- 7 Specifications
-
8 Detailed Description
- 8.1 Overview
- 8.2 Functional Block Diagram
- 8.3
Feature Description
- 8.3.1 Fixed Frequency Valley/Peak Current Mode Control with Slope Compensation
- 8.3.2 VCC Regulator and Optional BIAS Input
- 8.3.3 Enable/UVLO
- 8.3.4 Soft-Start
- 8.3.5 Overcurrent Protection
- 8.3.6 Average Input/Output Current Limiting
- 8.3.7 CCM/DCM Operation
- 8.3.8 Frequency and Synchronization (RT/SYNC)
- 8.3.9 Frequency Dithering
- 8.3.10 Output Overvoltage Protection (OVP)
- 8.3.11 Power Good (PGOOD)
- 8.3.12 Gm Error Amplifier
- 8.3.13 Integrated Gate Drivers
- 8.3.14 Thermal Shutdown
- 8.4 Device Functional Modes
-
9 Application and Implementation
- 9.1 Application Information
- 9.2
Typical Application
- 9.2.1 Design Requirements
- 9.2.2
Detailed Design Procedure
- 9.2.2.1 Frequency
- 9.2.2.2 VOUT
- 9.2.2.3 Inductor Selection
- 9.2.2.4 Output Capacitor
- 9.2.2.5 Input Capacitor
- 9.2.2.6 Sense Resistor (RSENSE)
- 9.2.2.7 Slope Compensation
- 9.2.2.8 UVLO
- 9.2.2.9 Soft-Start Capacitor
- 9.2.2.10 Dither Capacitor
- 9.2.2.11 MOSFETs QH1 and QL1
- 9.2.2.12 MOSFETs QH2 and QL2
- 9.2.2.13 Frequency Compensation
- 9.2.3 Application Curves
- 10Power Supply Recommendations
- 11Layout
- 12器件和文檔支持
- 13機(jī)械、封裝和可訂購信息
封裝選項
機(jī)械數(shù)據(jù) (封裝 | 引腳)
- PWP|28
散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)
- PWP|28
訂購信息
6 Pin Configuration and Functions
HTSSOP-28
PWP Package
Top View
Pin Functions
| PIN | DESCRIPTION | ||
|---|---|---|---|
| NO. | NAME | ||
| 1 | EN/UVLO | Enable pin. For EN/UVLO < 0.4 V, the LM5175-Q1 is in a low current shutdown mode. For 0.7 V < EN/UVLO < 1.23 V, the controller operates in standby mode in which the VCC regulator is enabled but the PWM controller is not switching. For EN/UVLO > 1.23 V, the PWM function is enabled, provided VCC exceeds the VCC UV threshold. | |
| 2 | VIN | The input supply pin to the IC. Connect VIN to a supply voltage between 3.5 V and 42 V. | |
| 3 | VISNS | VIN sense input. Connect to the input capacitor. | |
| 4 | MODE | Mode = GND, DCM, Hiccup Disabled (Set RMODE resistor to GND = 0 Ω) | |
| Mode = 1.00 V, DCM, Hiccup Enabled (Set RMODE resistor to GND = 49.9 kΩ) | |||
| Mode = 1.85 V, CCM, Hiccup Enabled (Set RMODE resistor to GND = 93.1 kΩ) | |||
| Mode = VCC, CCM, Hiccup Disabled (Set RMODE resistor to VCC = 0 Ω) | |||
| 5 | DITH | A capacitor connected between the DITH pin and AGND is charged and discharged with a 10 uA current source. As the voltage on the DITH pin ramps up and down the oscillator frequency is modulated between –5% and +5% of the nominal frequency set by the RT resistor. Grounding the DITH pin will disable the dithering feature. In the external Sync mode, the DITH pin voltage is ignored. | |
| 6 | RT/SYNC | Switching frequency programming pin. An external resistor is connected to the RT/SYNC pin and AGND to set the switching frequency. This pin can also be used to synchronize the PWM controller to an external clock. | |
| 7 | SLOPE | A capacitor connected between the SLOPE pin and AGND provides the slope compensation ramp for stable current mode operation in both buck and boost mode. | |
| 8 | SS | Soft-start programming pin. A capacitor between the SS pin and AGND pin programs soft-start time. | |
| 9 | COMP | Output of the error amplifier. An external RC network connected between COMP and AGND compensates the regulator feedback loop. | |
| 10 | AGND | Analog ground of the IC. | |
| 11 | FB | Feedback pin for output voltage regulation. Connect a resistor divider network from the output of the converter to the FB pin. | |
| 12 | VOSNS | VOUT sense input. Connect to the output capacitor. | |
| 13 14 |
ISNS(–) ISNS(+) |
Input or Output Current Sense Amplifier inputs. An optional current sense resistor connected between ISNS(+) and ISNS(–) can be located either on the input side or on the output side of the converter. If the sensed voltage across the ISNS(+) and ISNS(-) pins reaches 50 mV, a slow Constant Current (CC) control loop becomes active and starts discharging the soft-start capacitor to regulated the drop across ISNS(+) and ISNS(-) to 50 mV. Short ISNS(+) and ISNS(-) together to disable this feature. | |
| 15 | CSG | The negative or ground input to the PWM current sense amplifier. Connect directly to the low-side (ground) of the current sense resistor. | |
| 16 | CS | The positive input to the PWM current sense amplifier. | |
| 17 | PGOOD | Power Good open drain output. PGOOD is pulled low when FB is outside a 0.8 V ±10% regulation window. | |
| 18 28 |
SW2 SW1 |
The boost and the buck side switching nodes respectively. | |
| 19 27 |
HDRV2 HDRV1 |
Output of the high-side gate drivers. Connect directly to the gates of the high-side MOSFETs. | |
| 20 26 |
BOOT2 BOOT1 |
An external capacitor is required between the BOOT1, BOOT2 pins and the SW1, SW2 pins respectively to provide bias to the high-side MOSFET gate drivers. | |
| 21 25 |
LDRV2 LDRV1 |
Output of the low-side gate drivers. Connect directly to the gates of the low-side MOSFETs. | |
| 22 | PGND | Power ground of the IC. The high current ground connection to the low-side gate drivers. | |
| 23 | VCC | Output of the VCC bias regulator. Connect capacitor to ground. | |
| 24 | BIAS | Optional input to the VCC bias regulator. Powering VCC from an external supply instead of VIN can reduce power loss at high VIN. For VBIAS > 8 V, the VCC regulator draws power from the BIAS pin. The BIAS pin voltage must not exceed 40 V. | |
| - | PowerPAD™ | The PowerPAD should be soldered to the analog ground. If possible, use thermal vias to connect to a PCB ground plane for improved power dissipation. | |