ZHCSPF2B December 2021 – December 2024 LM5168 , LM5169
PRODUCTION DATA
- 1
- 1 特性
- 2 應用
- 3 說明
- 4 Device Comparison Table
- 5 Pin Configuration and Functions
- 6 Specifications
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3
Feature Description
- 7.3.1 Control Architecture
- 7.3.2 Internal VCC Regulator and Bootstrap Capacitor
- 7.3.3 Internal Soft Start
- 7.3.4 On-Time Generator
- 7.3.5 Current Limit
- 7.3.6 N-Channel Buck Switch and Driver
- 7.3.7 Synchronous Rectifier
- 7.3.8 Enable, Undervoltage Lockout (EN/UVLO)
- 7.3.9 Power Good (PGOOD)
- 7.3.10 Thermal Protection
- 7.4 Device Functional Modes
-
8 Application and Implementation
- 8.1 Application Information
- 8.2
Typical Fly-Buck? Converter Application
- 8.2.1 Design Requirements
- 8.2.2
Detailed Design Procedure
- 8.2.2.1 Switching Frequency (RT)
- 8.2.2.2 Transformer Selection
- 8.2.2.3 Output Capacitor Selection
- 8.2.2.4 Secondary Output Diode
- 8.2.2.5 Setting Output Voltage
- 8.2.2.6 Input Capacitor
- 8.2.2.7 Type-3 Ripple Network
- 8.2.2.8 CBST Selection
- 8.2.2.9 Minimum Secondary Output Load
- 8.2.2.10 Example Design Summary
- 8.2.3 Application Curves
- 8.3 Typical Buck Application
- 8.4 Power Supply Recommendations
- 8.5 Layout
- 9 Device and Documentation Support
- 10Revision History
- 11Mechanical, Packaging, and Orderable Information
封裝選項
機械數據 (封裝 | 引腳)
散熱焊盤機械數據 (封裝 | 引腳)
- DDA|8
訂購信息
5 Pin Configuration and Functions
Figure 5-1 8-Pin SO PowerPAD?Integrated
Circuit Package(Top View)
Figure 5-2 8-Pin WSON NGU Package (Top
View)Table 5-1 Pin Functions
| PIN | TYPE(1) | DESCRIPTION | |
|---|---|---|---|
| NO. | NAME | ||
| 1 | GND | G | Ground connection for internal circuits |
| 2 | VIN | P/I | Regulator supply input pin to the high-side power MOSFET and internal bias regulator. Connect directly to the input supply of the buck converter with short, low impedance paths. |
| 3 | EN/UVLO | I | Precision enable and undervoltage lockout (UVLO) programming pin. If the EN/UVLO rising voltage is below 1.1 V, the converter is in shutdown mode with all functions disabled. If the UVLO voltage is greater than 1.1 V and below 1.5 V, the converter is in standby mode with the internal VCC regulator operational and no switching. If the EN/UVLO voltage is above 1.5 V, the start-up sequence begins. |
| 4 | RT | I | On-time programming pin. A resistor between this pin and GND sets the buck switch on time. |
| 5 | FB | I | Feedback input of voltage regulation comparator |
| 6 | PGOOD | O | Power-good indicator. This pin is an open-drain output pin. Connect to a source voltage through an external pullup resistor between 10 kΩ to 100 kΩ. Connect to GND if the PGOOD feature is not needed. |
| 7 | BST | P/I | Bootstrap gate-drive supply. Required to connect a high-quality 2.2-nF X7R ceramic capacitor between BST and SW to bias the internal high-side gate driver. |
| 8 | SW | P | Switching node that is internally connected to the source of the high-side NMOS buck switch and the drain of the low-side NMOS synchronous rectifier. Connect to the switching node of the power inductor. |
| — | EP | — | Exposed pad of the package. No internal electrical connection. Solder the EP to the GND pin and connect to a large copper plane to reduce thermal resistance. |
(1) G = Ground, I = Input, O = Output, P = Power