ZHCSOQ8A August 2021 – October 2021 LM5158-Q1 , LM51581-Q1
PRODUCTION DATA
- 1 特性
- 2 應(yīng)用
- 3 說明
- 4 Revision History
- 5 說明（續(xù)）
- 6 Device Comparison Table
- 7 Pin Configuration and Functions
- 8 Specifications
-
9 Detailed Description
- 9.1 Overview
- 9.2 Functional Block Diagram
- 9.3
Feature Description
- 9.3.1 Line Undervoltage Lockout (EN/UVLO/SYNC Pin)
- 9.3.2 High Voltage VCC Regulator (BIAS, VCC Pin)
- 9.3.3 Soft Start (SS Pin)
- 9.3.4 Switching Frequency (RT Pin)
- 9.3.5 Dual Random Spread Spectrum – DRSS (MODE Pin)
- 9.3.6 Clock Synchronization (EN/UVLO/SYNC Pin)
- 9.3.7 Current Sense and Slope Compensation
- 9.3.8 Current Limit and Minimum On Time
- 9.3.9 Feedback and Error Amplifier (FB, COMP Pin)
- 9.3.10 Power-Good Indicator (PGOOD Pin)
- 9.3.11 Hiccup Mode Overload Protection (MODE Pin)
- 9.3.12 Maximum Duty Cycle Limit and Minimum Input Supply Voltage
- 9.3.13 Internal MOSFET (SW Pin)
- 9.3.14 Overvoltage Protection (OVP)
- 9.3.15 Thermal Shutdown (TSD)
- 9.4 Device Functional Modes
- 10Application and Implementation
- 11Power Supply Recommendations
- 12Layout
- 13Device and Documentation Support
- 14Mechanical, Packaging, and Orderable Information
封裝選項
機械數(shù)據(jù) (封裝 | 引腳)
- RTE|16
散熱焊盤機械數(shù)據(jù) (封裝 | 引腳)
- RTE|16
訂購信息
7 Pin Configuration and Functions
Figure 7-1 RTE
Package16-Pin WQFN With Wettable FlanksTop ViewTable 7-1 Pin Functions
| PIN | TYPE(1) | DESCRIPTION | |
|---|---|---|---|
| NO. | NAME | ||
| 1, 16 | PGND | P | Power ground pin. Source connection of the internal N-channel power MOSFET |
| 2 | VCC | P | Output of the internal VCC regulator and supply voltage input of the internal MOSFET driver. Connect a 1-μF ceramic bypass capacitor from this pin to PGND. |
| 3 | BIAS | P | Supply voltage input to the VCC regulator. Connect a bypass capacitor from this pin to PGND. |
| 4 | PGOOD | O | Power-good indicator. An open-drain output, which goes low if FB is below the undervoltage threshold (VUVTH). Connect a pullup resistor to the system voltage rail. |
| 5 | RT | I | Switching frequency setting pin. The switching frequency is programmed by a single resistor between RT and AGND. |
| 6 | EN/UVLO/SYNC | I | Enable pin. The converter shuts down when the pin is less than the enable threshold (VEN). |
| Undervoltage lockout programming pin. The converter start-up and shutdown levels can be programmed by connecting this pin to the supply voltage through a voltage divider. If using a programmable UVLO, connect the low-side UVLO resistor to AGND. This pin must not be left floating. Connect to the BIAS pin if not used. | |||
| External synchronization clock input pin. The internal clock can be synchronized to an external clock by applying a negative pulse signal into the pin. | |||
| 7 | AGND | G | Analog ground pin. Connect to the analog ground plane through a wide and short path. |
| 8 | COMP | O | Output of the internal transconductance error amplifier. Connect the loop compensation components between this pin and AGND. |
| 9 | FB | I | Inverting input of the error amplifier. Connect a voltage divider to set the output voltage in boost, SEPIC, or primary-side regulated flyback topologies. Connect the low-side feedback resistor as close to AGND as possible. |
| 10 | SS | I | Soft-start time programming pin. An external capacitor and an internal current source set the ramp rate of the internal error amplifier reference during soft start. Connect the ground connection of the capacitor to AGND. |
| 11 | MODE | I | MODE = 0 V or connect to AGND during initial power up: Hiccup mode protection is disabled and spread spectrum is disabled. |
| MODE = 370 mV or connect a 37.4-kΩ resistor between this pin and AGND during initial power up: Hiccup mode protection is enabled and spread spectrum is enabled. | |||
| MODE = 620 mV or connect a 62.0-kΩ resistor between this pin and AGND during initial power up: Hiccup mode protection is enabled and spread spectrum is disabled. | |||
| MODE > 1 V or connect a 100-kΩ resistor between this pin and AGND during initial power up: Hiccup mode protection is disabled and spread spectrum is enabled. | |||
| 13, 14 | SW | Switch pin. Drain connection of the internal N-channel power MOSFET | |
| 12, 15 | NC | — | No internal electrical contact |
| — | EP | — | Exposed pad of the package. The exposed pad must be connected to AGND and the large ground copper plane to decrease thermal resistance. |
(1) G = Ground, I = Input, O = Output, P = Power