ZHCSOB0A july 2021 – august 2023 LM5157
PRODUCTION DATA
- 1
- 1 特性
- 2 應用
- 3 說明
- 4 Revision History
- 5 Device Comparison Table
- 6 Pin Configuration and Functions
- 7 Specifications
-
8 Detailed Description
- 8.1 Overview
- 8.2 Functional Block Diagram
- 8.3
Feature Description
- 8.3.1 Line Undervoltage Lockout (UVLO/SYNC/EN Pin)
- 8.3.2 High Voltage VCC Regulator (BIAS, VCC Pin)
- 8.3.3 Soft Start (SS Pin)
- 8.3.4 Switching Frequency (RT Pin)
- 8.3.5 Dual Random Spread Spectrum – DRSS (MODE Pin)
- 8.3.6 Clock Synchronization (UVLO/SYNC/EN Pin)
- 8.3.7 Current Sense and Slope Compensation
- 8.3.8 Current Limit and Minimum On Time
- 8.3.9 Feedback and Error Amplifier (FB, COMP Pin)
- 8.3.10 Power-Good Indicator (PGOOD Pin)
- 8.3.11 Hiccup Mode Overload Protection (MODE Pin)
- 8.3.12 Maximum Duty Cycle Limit and Minimum Input Supply Voltage
- 8.3.13 Internal MOSFET (SW Pin)
- 8.3.14 Overvoltage Protection (OVP)
- 8.3.15 Thermal Shutdown (TSD)
- 8.4 Device Functional Modes
- 9 Application and Implementation
- 10Power Supply Recommendations
- 11Layout
- 12Device and Documentation Support
- 13Mechanical, Packaging, and Orderable Information
8.3.7 Current Sense and Slope Compensation
The device senses switch current which flows into the SW pin, and provides a fixed internal slope compensation ramp, helping prevent subharmonic oscillation at high duty cycle. The internal slope compensation ramp is added to the sensed switch current for the PWM operation, but no slope compensation ramp is added to the sensed inductor current for the current limit operation to provide an accurate peak current limit over the input supply voltage (see Figure 8-17).
Figure 8-17 Current Sensing and Slope Compensation
Figure 8-18 Current Sensing and Slope Compensation (a) at PWM Comparator Inputs
Figure 8-19 Current Sensing (b) at Current
Limit Comparator InputsUse Equation 6 to calculate the value of the peak slope voltage (VSLOPE).
where
- fSYNC is fRT if clock synchronization is not used
According to peak current mode control theory, the slope of the compensation ramp must be greater than half of the sensed inductor current falling slope to prevent subharmonic oscillation at high duty cycle. Therefore, the minimum amount of slope compensation in boost topology must satisfy the following inequality:
where
- VF is a forward voltage drop of D1, the external diode
Typically, 82% of the sensed inductor current falling slope is known as an optimal amount of the slope compensation. By increasing the margin to 1.6, the amount of slope compensation becomes close to the optimal amount.
If clock synchronization is not used, the fSW frequency equals the fRT frequency. If clock synchronization is used, the fSW frequency equals the fSYNC frequency.