ZHCSFB5D July 2016 – December 2017 LM5141-Q1
PRODUCTION DATA.
- 1 特性
- 2 應用
- 3 說明
- 4 修訂歷史記錄
- 5 Pin Configuration and Functions
- 6 Specifications
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3
Feature Description
- 7.3.1 High Voltage Start-up Regulator
- 7.3.2 VCC Regulator
- 7.3.3 Oscillator
- 7.3.4 Synchronization
- 7.3.5 Frequency Dithering (Spread Spectrum)
- 7.3.6 Enable
- 7.3.7 Power Good
- 7.3.8 Output Voltage
- 7.3.9 Current Sense
- 7.3.10 DCR Current Sensing
- 7.3.11 Error Amplifier and PWM Comparator
- 7.3.12 Slope Compensation
- 7.3.13 Hiccup Mode Current Limiting
- 7.3.14 Standby Mode
- 7.3.15 Soft Start
- 7.3.16 Diode Emulation
- 7.3.17 High- and Low-Side Drivers
-
8 Application and Implementation
- 8.1 Application Information
- 8.2 Typical Application
- 9 Power Supply Recommendations
- 10Layout
- 11器件和文檔支持
- 12機械、封裝和可訂購信息
8.2.2.3 Current Sense Resistor
When calculating the current sense resistor, the maximum output current capability (IOUT(MAX)) must be at least 20% higher than the required full load current to account for tolerances, ripple current, and load transients. For this example, 120% of the 6.41-A peak inductor current calculated in Inductor Calculation (IPK) is 7.69 A. The current sense resistor value can be calculated using:
where
- V(CS) is the 75 mV current limit threshold
The RSENSE value selected is 9 mΩ.
Carefully observe the PCB layout guidelines to ensure that noise and DC errors do not corrupt the differential current sense signals between the CS and VOUT pins. Place the sense resistor close to the devices with short, direct traces, creating Kelvin-sense connections between the current-sense resistor and the LM5141-Q1.
The propagation delays through the current limit comparator, logic, and external MOSFET gate drivers allow the peak current to increase above the calculated current limit threshold. For a propagation delay of tdly, the worst-case peak current through the inductor with the output shorted can be calculated from:
From Electrical Characteristics, tdly1 is typically 40 ns.
Once the peak current and the inductance parameters are known, the inductor can be chosen. Select an inductor with a saturation current greater than IpkSCKT (8.81 Apk).